target/i386: Use MMU_NESTED_IDX for vmload/vmsave
Use MMU_NESTED_IDX for each memory access, rather than just a single translation to physical. Adjust svm_save_seg and svm_load_seg to pass in mmu_idx. This removes the last use of get_hphys so remove it. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20221002172956.265735-7-richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Richard Henderson
Paolo Bonzini
parent
98281984a3
commit
726ea33531
@ -2387,8 +2387,6 @@ static inline bool ctl_has_irq(CPUX86State *env)
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return (env->int_ctl & V_IRQ_MASK) && (int_prio >= tpr);
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}
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hwaddr get_hphys(CPUState *cs, hwaddr gphys, MMUAccessType access_type,
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int *prot);
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#if defined(TARGET_X86_64) && \
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defined(CONFIG_USER_ONLY) && \
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defined(CONFIG_LINUX)
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@ -413,37 +413,6 @@ static G_NORETURN void raise_stage2(CPUX86State *env, TranslateFault *err,
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cpu_vmexit(env, SVM_EXIT_NPF, exit_info_1, retaddr);
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}
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hwaddr get_hphys(CPUState *cs, hwaddr gphys, MMUAccessType access_type,
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int *prot)
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{
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CPUX86State *env = cs->env_ptr;
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if (likely(!(env->hflags2 & HF2_NPT_MASK))) {
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return gphys;
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} else {
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TranslateParams in = {
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.addr = gphys,
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.cr3 = env->nested_cr3,
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.pg_mode = env->nested_pg_mode,
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.mmu_idx = MMU_USER_IDX,
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.access_type = access_type,
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.use_stage2 = false,
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};
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TranslateResult out;
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TranslateFault err;
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if (!mmu_translate(env, &in, &out, &err)) {
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err.stage2 = prot ? SVM_NPTEXIT_GPA : SVM_NPTEXIT_GPT;
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raise_stage2(env, &err, env->retaddr);
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}
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if (prot) {
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*prot &= out.prot;
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}
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return out.paddr;
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}
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}
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static bool get_physical_address(CPUX86State *env, vaddr addr,
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MMUAccessType access_type, int mmu_idx,
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TranslateResult *out, TranslateFault *err)
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@ -27,19 +27,19 @@
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/* Secure Virtual Machine helpers */
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static inline void svm_save_seg(CPUX86State *env, hwaddr addr,
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const SegmentCache *sc)
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static void svm_save_seg(CPUX86State *env, int mmu_idx, hwaddr addr,
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const SegmentCache *sc)
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{
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CPUState *cs = env_cpu(env);
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x86_stw_phys(cs, addr + offsetof(struct vmcb_seg, selector),
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sc->selector);
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x86_stq_phys(cs, addr + offsetof(struct vmcb_seg, base),
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sc->base);
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x86_stl_phys(cs, addr + offsetof(struct vmcb_seg, limit),
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sc->limit);
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x86_stw_phys(cs, addr + offsetof(struct vmcb_seg, attrib),
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((sc->flags >> 8) & 0xff) | ((sc->flags >> 12) & 0x0f00));
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cpu_stw_mmuidx_ra(env, addr + offsetof(struct vmcb_seg, selector),
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sc->selector, mmu_idx, 0);
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cpu_stq_mmuidx_ra(env, addr + offsetof(struct vmcb_seg, base),
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sc->base, mmu_idx, 0);
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cpu_stl_mmuidx_ra(env, addr + offsetof(struct vmcb_seg, limit),
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sc->limit, mmu_idx, 0);
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cpu_stw_mmuidx_ra(env, addr + offsetof(struct vmcb_seg, attrib),
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((sc->flags >> 8) & 0xff)
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| ((sc->flags >> 12) & 0x0f00),
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mmu_idx, 0);
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}
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/*
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@ -52,29 +52,36 @@ static inline void svm_canonicalization(CPUX86State *env, target_ulong *seg_base
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*seg_base = ((((long) *seg_base) << shift_amt) >> shift_amt);
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}
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static inline void svm_load_seg(CPUX86State *env, hwaddr addr,
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SegmentCache *sc)
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static void svm_load_seg(CPUX86State *env, int mmu_idx, hwaddr addr,
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SegmentCache *sc)
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{
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CPUState *cs = env_cpu(env);
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unsigned int flags;
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sc->selector = x86_lduw_phys(cs,
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addr + offsetof(struct vmcb_seg, selector));
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sc->base = x86_ldq_phys(cs, addr + offsetof(struct vmcb_seg, base));
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sc->limit = x86_ldl_phys(cs, addr + offsetof(struct vmcb_seg, limit));
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flags = x86_lduw_phys(cs, addr + offsetof(struct vmcb_seg, attrib));
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sc->selector =
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cpu_lduw_mmuidx_ra(env, addr + offsetof(struct vmcb_seg, selector),
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mmu_idx, 0);
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sc->base =
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cpu_ldq_mmuidx_ra(env, addr + offsetof(struct vmcb_seg, base),
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mmu_idx, 0);
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sc->limit =
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cpu_ldl_mmuidx_ra(env, addr + offsetof(struct vmcb_seg, limit),
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mmu_idx, 0);
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flags =
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cpu_lduw_mmuidx_ra(env, addr + offsetof(struct vmcb_seg, attrib),
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mmu_idx, 0);
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sc->flags = ((flags & 0xff) << 8) | ((flags & 0x0f00) << 12);
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svm_canonicalization(env, &sc->base);
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}
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static inline void svm_load_seg_cache(CPUX86State *env, hwaddr addr,
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int seg_reg)
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static void svm_load_seg_cache(CPUX86State *env, int mmu_idx,
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hwaddr addr, int seg_reg)
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{
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SegmentCache sc1, *sc = &sc1;
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SegmentCache sc;
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svm_load_seg(env, addr, sc);
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cpu_x86_load_seg_cache(env, seg_reg, sc->selector,
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sc->base, sc->limit, sc->flags);
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svm_load_seg(env, mmu_idx, addr, &sc);
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cpu_x86_load_seg_cache(env, seg_reg, sc.selector,
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sc.base, sc.limit, sc.flags);
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}
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static inline bool is_efer_invalid_state (CPUX86State *env)
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@ -199,13 +206,17 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend)
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env->vm_hsave + offsetof(struct vmcb, save.rflags),
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cpu_compute_eflags(env));
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svm_save_seg(env, env->vm_hsave + offsetof(struct vmcb, save.es),
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svm_save_seg(env, MMU_PHYS_IDX,
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env->vm_hsave + offsetof(struct vmcb, save.es),
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&env->segs[R_ES]);
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svm_save_seg(env, env->vm_hsave + offsetof(struct vmcb, save.cs),
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svm_save_seg(env, MMU_PHYS_IDX,
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env->vm_hsave + offsetof(struct vmcb, save.cs),
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&env->segs[R_CS]);
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svm_save_seg(env, env->vm_hsave + offsetof(struct vmcb, save.ss),
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svm_save_seg(env, MMU_PHYS_IDX,
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env->vm_hsave + offsetof(struct vmcb, save.ss),
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&env->segs[R_SS]);
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svm_save_seg(env, env->vm_hsave + offsetof(struct vmcb, save.ds),
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svm_save_seg(env, MMU_PHYS_IDX,
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env->vm_hsave + offsetof(struct vmcb, save.ds),
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&env->segs[R_DS]);
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x86_stq_phys(cs, env->vm_hsave + offsetof(struct vmcb, save.rip),
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@ -325,18 +336,18 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend)
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save.rflags)),
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~(CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C | DF_MASK));
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svm_load_seg_cache(env, env->vm_vmcb + offsetof(struct vmcb, save.es),
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R_ES);
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svm_load_seg_cache(env, env->vm_vmcb + offsetof(struct vmcb, save.cs),
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R_CS);
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svm_load_seg_cache(env, env->vm_vmcb + offsetof(struct vmcb, save.ss),
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R_SS);
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svm_load_seg_cache(env, env->vm_vmcb + offsetof(struct vmcb, save.ds),
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R_DS);
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svm_load_seg(env, env->vm_vmcb + offsetof(struct vmcb, save.idtr),
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&env->idt);
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svm_load_seg(env, env->vm_vmcb + offsetof(struct vmcb, save.gdtr),
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&env->gdt);
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svm_load_seg_cache(env, MMU_PHYS_IDX,
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env->vm_vmcb + offsetof(struct vmcb, save.es), R_ES);
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svm_load_seg_cache(env, MMU_PHYS_IDX,
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env->vm_vmcb + offsetof(struct vmcb, save.cs), R_CS);
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svm_load_seg_cache(env, MMU_PHYS_IDX,
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env->vm_vmcb + offsetof(struct vmcb, save.ss), R_SS);
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svm_load_seg_cache(env, MMU_PHYS_IDX,
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env->vm_vmcb + offsetof(struct vmcb, save.ds), R_DS);
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svm_load_seg(env, MMU_PHYS_IDX,
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env->vm_vmcb + offsetof(struct vmcb, save.idtr), &env->idt);
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svm_load_seg(env, MMU_PHYS_IDX,
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env->vm_vmcb + offsetof(struct vmcb, save.gdtr), &env->gdt);
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env->eip = x86_ldq_phys(cs,
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env->vm_vmcb + offsetof(struct vmcb, save.rip));
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@ -451,9 +462,8 @@ void helper_vmmcall(CPUX86State *env)
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void helper_vmload(CPUX86State *env, int aflag)
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{
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CPUState *cs = env_cpu(env);
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int mmu_idx = MMU_PHYS_IDX;
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target_ulong addr;
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int prot;
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cpu_svm_check_intercept_param(env, SVM_EXIT_VMLOAD, 0, GETPC());
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@ -464,43 +474,52 @@ void helper_vmload(CPUX86State *env, int aflag)
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}
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if (virtual_vm_load_save_enabled(env, SVM_EXIT_VMLOAD, GETPC())) {
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addr = get_hphys(cs, addr, MMU_DATA_LOAD, &prot);
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mmu_idx = MMU_NESTED_IDX;
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}
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qemu_log_mask(CPU_LOG_TB_IN_ASM, "vmload! " TARGET_FMT_lx
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"\nFS: %016" PRIx64 " | " TARGET_FMT_lx "\n",
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addr, x86_ldq_phys(cs, addr + offsetof(struct vmcb,
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save.fs.base)),
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env->segs[R_FS].base);
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svm_load_seg_cache(env, addr + offsetof(struct vmcb, save.fs), R_FS);
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svm_load_seg_cache(env, addr + offsetof(struct vmcb, save.gs), R_GS);
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svm_load_seg(env, addr + offsetof(struct vmcb, save.tr), &env->tr);
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svm_load_seg(env, addr + offsetof(struct vmcb, save.ldtr), &env->ldt);
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svm_load_seg_cache(env, mmu_idx,
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addr + offsetof(struct vmcb, save.fs), R_FS);
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svm_load_seg_cache(env, mmu_idx,
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addr + offsetof(struct vmcb, save.gs), R_GS);
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svm_load_seg(env, mmu_idx,
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addr + offsetof(struct vmcb, save.tr), &env->tr);
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svm_load_seg(env, mmu_idx,
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addr + offsetof(struct vmcb, save.ldtr), &env->ldt);
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#ifdef TARGET_X86_64
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env->kernelgsbase = x86_ldq_phys(cs, addr + offsetof(struct vmcb,
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save.kernel_gs_base));
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env->lstar = x86_ldq_phys(cs, addr + offsetof(struct vmcb, save.lstar));
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env->cstar = x86_ldq_phys(cs, addr + offsetof(struct vmcb, save.cstar));
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env->fmask = x86_ldq_phys(cs, addr + offsetof(struct vmcb, save.sfmask));
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env->kernelgsbase =
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cpu_ldq_mmuidx_ra(env,
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addr + offsetof(struct vmcb, save.kernel_gs_base),
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mmu_idx, 0);
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env->lstar =
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cpu_ldq_mmuidx_ra(env, addr + offsetof(struct vmcb, save.lstar),
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mmu_idx, 0);
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env->cstar =
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cpu_ldq_mmuidx_ra(env, addr + offsetof(struct vmcb, save.cstar),
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mmu_idx, 0);
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env->fmask =
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cpu_ldq_mmuidx_ra(env, addr + offsetof(struct vmcb, save.sfmask),
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mmu_idx, 0);
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svm_canonicalization(env, &env->kernelgsbase);
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#endif
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env->star = x86_ldq_phys(cs, addr + offsetof(struct vmcb, save.star));
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env->sysenter_cs = x86_ldq_phys(cs,
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addr + offsetof(struct vmcb, save.sysenter_cs));
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env->sysenter_esp = x86_ldq_phys(cs, addr + offsetof(struct vmcb,
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save.sysenter_esp));
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env->sysenter_eip = x86_ldq_phys(cs, addr + offsetof(struct vmcb,
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save.sysenter_eip));
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env->star =
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cpu_ldq_mmuidx_ra(env, addr + offsetof(struct vmcb, save.star),
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mmu_idx, 0);
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env->sysenter_cs =
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cpu_ldq_mmuidx_ra(env, addr + offsetof(struct vmcb, save.sysenter_cs),
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mmu_idx, 0);
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env->sysenter_esp =
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cpu_ldq_mmuidx_ra(env, addr + offsetof(struct vmcb, save.sysenter_esp),
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mmu_idx, 0);
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env->sysenter_eip =
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cpu_ldq_mmuidx_ra(env, addr + offsetof(struct vmcb, save.sysenter_eip),
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mmu_idx, 0);
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}
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void helper_vmsave(CPUX86State *env, int aflag)
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{
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CPUState *cs = env_cpu(env);
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int mmu_idx = MMU_PHYS_IDX;
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target_ulong addr;
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int prot;
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cpu_svm_check_intercept_param(env, SVM_EXIT_VMSAVE, 0, GETPC());
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@ -511,38 +530,36 @@ void helper_vmsave(CPUX86State *env, int aflag)
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}
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if (virtual_vm_load_save_enabled(env, SVM_EXIT_VMSAVE, GETPC())) {
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addr = get_hphys(cs, addr, MMU_DATA_STORE, &prot);
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mmu_idx = MMU_NESTED_IDX;
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}
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qemu_log_mask(CPU_LOG_TB_IN_ASM, "vmsave! " TARGET_FMT_lx
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"\nFS: %016" PRIx64 " | " TARGET_FMT_lx "\n",
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addr, x86_ldq_phys(cs,
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addr + offsetof(struct vmcb, save.fs.base)),
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env->segs[R_FS].base);
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svm_save_seg(env, addr + offsetof(struct vmcb, save.fs),
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svm_save_seg(env, mmu_idx, addr + offsetof(struct vmcb, save.fs),
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&env->segs[R_FS]);
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svm_save_seg(env, addr + offsetof(struct vmcb, save.gs),
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svm_save_seg(env, mmu_idx, addr + offsetof(struct vmcb, save.gs),
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&env->segs[R_GS]);
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svm_save_seg(env, addr + offsetof(struct vmcb, save.tr),
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svm_save_seg(env, mmu_idx, addr + offsetof(struct vmcb, save.tr),
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&env->tr);
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svm_save_seg(env, addr + offsetof(struct vmcb, save.ldtr),
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svm_save_seg(env, mmu_idx, addr + offsetof(struct vmcb, save.ldtr),
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&env->ldt);
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#ifdef TARGET_X86_64
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x86_stq_phys(cs, addr + offsetof(struct vmcb, save.kernel_gs_base),
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env->kernelgsbase);
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x86_stq_phys(cs, addr + offsetof(struct vmcb, save.lstar), env->lstar);
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x86_stq_phys(cs, addr + offsetof(struct vmcb, save.cstar), env->cstar);
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x86_stq_phys(cs, addr + offsetof(struct vmcb, save.sfmask), env->fmask);
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cpu_stq_mmuidx_ra(env, addr + offsetof(struct vmcb, save.kernel_gs_base),
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env->kernelgsbase, mmu_idx, 0);
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cpu_stq_mmuidx_ra(env, addr + offsetof(struct vmcb, save.lstar),
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env->lstar, mmu_idx, 0);
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cpu_stq_mmuidx_ra(env, addr + offsetof(struct vmcb, save.cstar),
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env->cstar, mmu_idx, 0);
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cpu_stq_mmuidx_ra(env, addr + offsetof(struct vmcb, save.sfmask),
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env->fmask, mmu_idx, 0);
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#endif
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x86_stq_phys(cs, addr + offsetof(struct vmcb, save.star), env->star);
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x86_stq_phys(cs,
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addr + offsetof(struct vmcb, save.sysenter_cs), env->sysenter_cs);
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x86_stq_phys(cs, addr + offsetof(struct vmcb, save.sysenter_esp),
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env->sysenter_esp);
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x86_stq_phys(cs, addr + offsetof(struct vmcb, save.sysenter_eip),
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env->sysenter_eip);
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cpu_stq_mmuidx_ra(env, addr + offsetof(struct vmcb, save.star),
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env->star, mmu_idx, 0);
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cpu_stq_mmuidx_ra(env, addr + offsetof(struct vmcb, save.sysenter_cs),
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env->sysenter_cs, mmu_idx, 0);
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cpu_stq_mmuidx_ra(env, addr + offsetof(struct vmcb, save.sysenter_esp),
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env->sysenter_esp, mmu_idx, 0);
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cpu_stq_mmuidx_ra(env, addr + offsetof(struct vmcb, save.sysenter_eip),
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env->sysenter_eip, mmu_idx, 0);
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}
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void helper_stgi(CPUX86State *env)
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@ -725,13 +742,17 @@ void do_vmexit(CPUX86State *env)
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tlb_flush_by_mmuidx(cs, 1 << MMU_NESTED_IDX);
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/* Save the VM state in the vmcb */
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svm_save_seg(env, env->vm_vmcb + offsetof(struct vmcb, save.es),
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svm_save_seg(env, MMU_PHYS_IDX,
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env->vm_vmcb + offsetof(struct vmcb, save.es),
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&env->segs[R_ES]);
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svm_save_seg(env, env->vm_vmcb + offsetof(struct vmcb, save.cs),
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svm_save_seg(env, MMU_PHYS_IDX,
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env->vm_vmcb + offsetof(struct vmcb, save.cs),
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&env->segs[R_CS]);
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svm_save_seg(env, env->vm_vmcb + offsetof(struct vmcb, save.ss),
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svm_save_seg(env, MMU_PHYS_IDX,
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env->vm_vmcb + offsetof(struct vmcb, save.ss),
|
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&env->segs[R_SS]);
|
||||
svm_save_seg(env, env->vm_vmcb + offsetof(struct vmcb, save.ds),
|
||||
svm_save_seg(env, MMU_PHYS_IDX,
|
||||
env->vm_vmcb + offsetof(struct vmcb, save.ds),
|
||||
&env->segs[R_DS]);
|
||||
|
||||
x86_stq_phys(cs, env->vm_vmcb + offsetof(struct vmcb, save.gdtr.base),
|
||||
@ -812,14 +833,14 @@ void do_vmexit(CPUX86State *env)
|
||||
~(CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C | DF_MASK |
|
||||
VM_MASK));
|
||||
|
||||
svm_load_seg_cache(env, env->vm_hsave + offsetof(struct vmcb, save.es),
|
||||
R_ES);
|
||||
svm_load_seg_cache(env, env->vm_hsave + offsetof(struct vmcb, save.cs),
|
||||
R_CS);
|
||||
svm_load_seg_cache(env, env->vm_hsave + offsetof(struct vmcb, save.ss),
|
||||
R_SS);
|
||||
svm_load_seg_cache(env, env->vm_hsave + offsetof(struct vmcb, save.ds),
|
||||
R_DS);
|
||||
svm_load_seg_cache(env, MMU_PHYS_IDX,
|
||||
env->vm_hsave + offsetof(struct vmcb, save.es), R_ES);
|
||||
svm_load_seg_cache(env, MMU_PHYS_IDX,
|
||||
env->vm_hsave + offsetof(struct vmcb, save.cs), R_CS);
|
||||
svm_load_seg_cache(env, MMU_PHYS_IDX,
|
||||
env->vm_hsave + offsetof(struct vmcb, save.ss), R_SS);
|
||||
svm_load_seg_cache(env, MMU_PHYS_IDX,
|
||||
env->vm_hsave + offsetof(struct vmcb, save.ds), R_DS);
|
||||
|
||||
env->eip = x86_ldq_phys(cs,
|
||||
env->vm_hsave + offsetof(struct vmcb, save.rip));
|
||||
|
||||
Loading…
Reference in New Issue
Block a user