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target/hexagon: rename aliased register HEX_REG_P3_0 

The patch renames the identifier of the 32bit register
HEX_REG_P3_0 to HEX_REG_P3_0_ALIASED.

This change is to intended to provide some warning that
HEX_REG_P3_0 is an aliased register which has multiple
representations in CPU state and therefore might require
special handling in some contexts. The hope is to prevent
accidental misuse of this register e.g the issue reported
for the signals tests failure [here][1].

[1]: https://lists.gnu.org/archive/html/qemu-devel/2021-11/msg01102.html

Signed-off-by: Mukilan Thiyagarajan <quic_mthiyaga@quicinc.com>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Taylor Simpson <tsimpson@quicinc.com>
Message-Id: <20221229092006.10709-3-quic_mthiyaga@quicinc.com>
This commit is contained in:
Mukilan Thiyagarajan 2022-12-29 14:50:06 +05:30 committed by Taylor Simpson
parent c979d901c8
commit 72895676e7
3 changed files with 10 additions and 10 deletions
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6
target/hexagon/cpu.c
View File

@ -86,7 +86,7 @@ static target_ulong adjust_stack_ptrs(CPUHexagonState *env, target_ulong addr)
return addr; return addr;
} }
/* HEX_REG_P3_0 (aka C4) is an alias for the predicate registers */ /* HEX_REG_P3_0_ALIASED (aka C4) is an alias for the predicate registers */
static target_ulong read_p3_0(CPUHexagonState *env) static target_ulong read_p3_0(CPUHexagonState *env)
{ {
int32_t control_reg = 0; int32_t control_reg = 0;
@ -102,7 +102,7 @@ static void print_reg(FILE *f, CPUHexagonState *env, int regnum)
{ {
target_ulong value; target_ulong value;
if (regnum == HEX_REG_P3_0) { if (regnum == HEX_REG_P3_0_ALIASED) {
value = read_p3_0(env); value = read_p3_0(env);
} else { } else {
value = regnum < 32 ? adjust_stack_ptrs(env, env->gpr[regnum]) value = regnum < 32 ? adjust_stack_ptrs(env, env->gpr[regnum])
@ -198,7 +198,7 @@ static void hexagon_dump(CPUHexagonState *env, FILE *f, int flags)
print_reg(f, env, HEX_REG_M0); print_reg(f, env, HEX_REG_M0);
print_reg(f, env, HEX_REG_M1); print_reg(f, env, HEX_REG_M1);
print_reg(f, env, HEX_REG_USR); print_reg(f, env, HEX_REG_USR);
print_reg(f, env, HEX_REG_P3_0); print_reg(f, env, HEX_REG_P3_0_ALIASED);
print_reg(f, env, HEX_REG_GP); print_reg(f, env, HEX_REG_GP);
print_reg(f, env, HEX_REG_UGP); print_reg(f, env, HEX_REG_UGP);
print_reg(f, env, HEX_REG_PC); print_reg(f, env, HEX_REG_PC);

12
target/hexagon/genptr.c
View File

@ -163,7 +163,7 @@ static inline void gen_read_p3_0(TCGv control_reg)
/* /*
* Certain control registers require special handling on read * Certain control registers require special handling on read
* HEX_REG_P3_0 aliased to the predicate registers * HEX_REG_P3_0_ALIASED aliased to the predicate registers
* -> concat the 4 predicate registers together * -> concat the 4 predicate registers together
* HEX_REG_PC actual value stored in DisasContext * HEX_REG_PC actual value stored in DisasContext
* -> assign from ctx->base.pc_next * -> assign from ctx->base.pc_next
@ -173,7 +173,7 @@ static inline void gen_read_p3_0(TCGv control_reg)
static inline void gen_read_ctrl_reg(DisasContext *ctx, const int reg_num, static inline void gen_read_ctrl_reg(DisasContext *ctx, const int reg_num,
TCGv dest) TCGv dest)
{ {
if (reg_num == HEX_REG_P3_0) { if (reg_num == HEX_REG_P3_0_ALIASED) {
gen_read_p3_0(dest); gen_read_p3_0(dest);
} else if (reg_num == HEX_REG_PC) { } else if (reg_num == HEX_REG_PC) {
tcg_gen_movi_tl(dest, ctx->base.pc_next); tcg_gen_movi_tl(dest, ctx->base.pc_next);
@ -194,7 +194,7 @@ static inline void gen_read_ctrl_reg(DisasContext *ctx, const int reg_num,
static inline void gen_read_ctrl_reg_pair(DisasContext *ctx, const int reg_num, static inline void gen_read_ctrl_reg_pair(DisasContext *ctx, const int reg_num,
TCGv_i64 dest) TCGv_i64 dest)
{ {
if (reg_num == HEX_REG_P3_0) { if (reg_num == HEX_REG_P3_0_ALIASED) {
TCGv p3_0 = tcg_temp_new(); TCGv p3_0 = tcg_temp_new();
gen_read_p3_0(p3_0); gen_read_p3_0(p3_0);
tcg_gen_concat_i32_i64(dest, p3_0, hex_gpr[reg_num + 1]); tcg_gen_concat_i32_i64(dest, p3_0, hex_gpr[reg_num + 1]);
@ -238,7 +238,7 @@ static void gen_write_p3_0(DisasContext *ctx, TCGv control_reg)
/* /*
* Certain control registers require special handling on write * Certain control registers require special handling on write
* HEX_REG_P3_0 aliased to the predicate registers * HEX_REG_P3_0_ALIASED aliased to the predicate registers
* -> break the value across 4 predicate registers * -> break the value across 4 predicate registers
* HEX_REG_QEMU_*_CNT changes in current TB in DisasContext * HEX_REG_QEMU_*_CNT changes in current TB in DisasContext
* -> clear the changes * -> clear the changes
@ -246,7 +246,7 @@ static void gen_write_p3_0(DisasContext *ctx, TCGv control_reg)
static inline void gen_write_ctrl_reg(DisasContext *ctx, int reg_num, static inline void gen_write_ctrl_reg(DisasContext *ctx, int reg_num,
TCGv val) TCGv val)
{ {
if (reg_num == HEX_REG_P3_0) { if (reg_num == HEX_REG_P3_0_ALIASED) {
gen_write_p3_0(ctx, val); gen_write_p3_0(ctx, val);
} else { } else {
gen_log_reg_write(reg_num, val); gen_log_reg_write(reg_num, val);
@ -266,7 +266,7 @@ static inline void gen_write_ctrl_reg(DisasContext *ctx, int reg_num,
static inline void gen_write_ctrl_reg_pair(DisasContext *ctx, int reg_num, static inline void gen_write_ctrl_reg_pair(DisasContext *ctx, int reg_num,
TCGv_i64 val) TCGv_i64 val)
{ {
if (reg_num == HEX_REG_P3_0) { if (reg_num == HEX_REG_P3_0_ALIASED) {
TCGv val32 = tcg_temp_new(); TCGv val32 = tcg_temp_new();
tcg_gen_extrl_i64_i32(val32, val); tcg_gen_extrl_i64_i32(val32, val);
gen_write_p3_0(ctx, val32); gen_write_p3_0(ctx, val32);

2
target/hexagon/hex_regs.h
View File

@ -58,7 +58,7 @@ enum {
HEX_REG_LC0 = 33, HEX_REG_LC0 = 33,
HEX_REG_SA1 = 34, HEX_REG_SA1 = 34,
HEX_REG_LC1 = 35, HEX_REG_LC1 = 35,
HEX_REG_P3_0 = 36, HEX_REG_P3_0_ALIASED = 36,
HEX_REG_M0 = 38, HEX_REG_M0 = 38,
HEX_REG_M1 = 39, HEX_REG_M1 = 39,
HEX_REG_USR = 40, HEX_REG_USR = 40,