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ppc/ppc405: QOM'ify OPBA

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The OPB arbitrer is currently modeled as a simple SysBus device with a
unique memory region.

Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
[balaton: ppc4xx_dcr_register changes]
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-Id: <38476bc43d2332db2f09dbede9eff5234d6ce217.1660746880.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
This commit is contained in:
Cédric Le Goater 2022-08-17 17:08:26 +02:00 committed by Daniel Henrique Barboza
parent 415a6333d4
commit 72beecc20c
3 changed files with 41 additions and 21 deletions
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12
hw/ppc/ppc405.h
View File

@ -63,6 +63,17 @@ struct ppc4xx_bd_info_t {
uint32_t bi_iic_fast[2];
};
/* OPB arbitrer */
#define TYPE_PPC405_OPBA "ppc405-opba"
OBJECT_DECLARE_SIMPLE_TYPE(Ppc405OpbaState, PPC405_OPBA);
struct Ppc405OpbaState {
SysBusDevice parent_obj;
MemoryRegion io;
uint8_t cr;
uint8_t pr;
};
/* Peripheral controller */
#define TYPE_PPC405_EBC "ppc405-ebc"
OBJECT_DECLARE_SIMPLE_TYPE(Ppc405EbcState, PPC405_EBC);
@ -208,6 +219,7 @@ struct Ppc405SoCState {
Ppc405GpioState gpio;
Ppc405DmaState dma;
Ppc405EbcState ebc;
Ppc405OpbaState opba;
};
/* PowerPC 405 core */

49
hw/ppc/ppc405_uc.c
View File

@ -310,16 +310,9 @@ static void ppc4xx_pob_init(CPUPPCState *env)
/*****************************************************************************/
/* OPB arbitrer */
typedef struct ppc4xx_opba_t ppc4xx_opba_t;
struct ppc4xx_opba_t {
MemoryRegion io;
uint8_t cr;
uint8_t pr;
};
static uint64_t opba_readb(void *opaque, hwaddr addr, unsigned size)
{
ppc4xx_opba_t *opba = opaque;
Ppc405OpbaState *opba = opaque;
uint32_t ret;
switch (addr) {
@ -341,7 +334,7 @@ static uint64_t opba_readb(void *opaque, hwaddr addr, unsigned size)
static void opba_writeb(void *opaque, hwaddr addr, uint64_t value,
unsigned size)
{
ppc4xx_opba_t *opba = opaque;
Ppc405OpbaState *opba = opaque;
trace_opba_writeb(addr, value);
@ -366,25 +359,30 @@ static const MemoryRegionOps opba_ops = {
.endianness = DEVICE_BIG_ENDIAN,
};
static void ppc4xx_opba_reset (void *opaque)
static void ppc405_opba_reset(DeviceState *dev)
{
ppc4xx_opba_t *opba;
Ppc405OpbaState *opba = PPC405_OPBA(dev);
opba = opaque;
opba->cr = 0x00; /* No dynamic priorities - park disabled */
opba->pr = 0x11;
}
static void ppc4xx_opba_init(hwaddr base)
static void ppc405_opba_realize(DeviceState *dev, Error **errp)
{
ppc4xx_opba_t *opba;
Ppc405OpbaState *s = PPC405_OPBA(dev);
trace_opba_init(base);
memory_region_init_io(&s->io, OBJECT(s), &opba_ops, s, "opba", 2);
sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->io);
}
opba = g_new0(ppc4xx_opba_t, 1);
memory_region_init_io(&opba->io, NULL, &opba_ops, opba, "opba", 0x002);
memory_region_add_subregion(get_system_memory(), base, &opba->io);
qemu_register_reset(ppc4xx_opba_reset, opba);
static void ppc405_opba_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
dc->realize = ppc405_opba_realize;
dc->reset = ppc405_opba_reset;
/* Reason: only works as function of a ppc4xx SoC */
dc->user_creatable = false;
}
/*****************************************************************************/
@ -1373,6 +1371,8 @@ static void ppc405_soc_instance_init(Object *obj)
object_initialize_child(obj, "dma", &s->dma, TYPE_PPC405_DMA);
object_initialize_child(obj, "ebc", &s->ebc, TYPE_PPC405_EBC);
object_initialize_child(obj, "opba", &s->opba, TYPE_PPC405_OPBA);
}
static void ppc405_reset(void *opaque)
@ -1410,7 +1410,11 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
ppc4xx_pob_init(env);
/* OBP arbitrer */
ppc4xx_opba_init(0xef600600);
sbd = SYS_BUS_DEVICE(&s->opba);
if (!sysbus_realize(sbd, errp)) {
return;
}
sysbus_mmio_map(sbd, 0, 0xef600600);
/* Universal interrupt controller */
s->uic = qdev_new(TYPE_PPC_UIC);
@ -1523,6 +1527,11 @@ static void ppc405_soc_class_init(ObjectClass *oc, void *data)
static const TypeInfo ppc405_types[] = {
{
.name = TYPE_PPC405_OPBA,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(Ppc405OpbaState),
.class_init = ppc405_opba_class_init,
}, {
.name = TYPE_PPC405_EBC,
.parent = TYPE_PPC4xx_DCR_DEVICE,
.instance_size = sizeof(Ppc405EbcState),

1
hw/ppc/trace-events
View File

@ -161,7 +161,6 @@ ppc440_pcix_reg_write(uint64_t addr, uint32_t val, uint32_t size) "addr 0x%" PRI
# ppc405_boards.c
opba_readb(uint64_t addr, uint32_t val) "addr 0x%" PRIx64 " = 0x%" PRIx32
opba_writeb(uint64_t addr, uint64_t val) "addr 0x%" PRIx64 " = 0x%" PRIx64
opba_init(uint64_t addr) "offet 0x%" PRIx64
ppc405_gpio_read(uint64_t addr, uint32_t size) "addr 0x%" PRIx64 " size %d"
ppc405_gpio_write(uint64_t addr, uint32_t size, uint64_t val) "addr 0x%" PRIx64 " size %d = 0x%" PRIx64