ppc/ppc405: QOM'ify OPBA
The OPB arbitrer is currently modeled as a simple SysBus device with a unique memory region. Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> [balaton: ppc4xx_dcr_register changes] Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Message-Id: <38476bc43d2332db2f09dbede9eff5234d6ce217.1660746880.git.balaton@eik.bme.hu> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
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@ -63,6 +63,17 @@ struct ppc4xx_bd_info_t {
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uint32_t bi_iic_fast[2];
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uint32_t bi_iic_fast[2];
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};
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};
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/* OPB arbitrer */
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#define TYPE_PPC405_OPBA "ppc405-opba"
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OBJECT_DECLARE_SIMPLE_TYPE(Ppc405OpbaState, PPC405_OPBA);
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struct Ppc405OpbaState {
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SysBusDevice parent_obj;
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MemoryRegion io;
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uint8_t cr;
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uint8_t pr;
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};
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/* Peripheral controller */
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/* Peripheral controller */
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#define TYPE_PPC405_EBC "ppc405-ebc"
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#define TYPE_PPC405_EBC "ppc405-ebc"
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OBJECT_DECLARE_SIMPLE_TYPE(Ppc405EbcState, PPC405_EBC);
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OBJECT_DECLARE_SIMPLE_TYPE(Ppc405EbcState, PPC405_EBC);
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@ -208,6 +219,7 @@ struct Ppc405SoCState {
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Ppc405GpioState gpio;
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Ppc405GpioState gpio;
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Ppc405DmaState dma;
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Ppc405DmaState dma;
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Ppc405EbcState ebc;
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Ppc405EbcState ebc;
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Ppc405OpbaState opba;
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};
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};
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/* PowerPC 405 core */
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/* PowerPC 405 core */
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@ -310,16 +310,9 @@ static void ppc4xx_pob_init(CPUPPCState *env)
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/*****************************************************************************/
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/*****************************************************************************/
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/* OPB arbitrer */
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/* OPB arbitrer */
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typedef struct ppc4xx_opba_t ppc4xx_opba_t;
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struct ppc4xx_opba_t {
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MemoryRegion io;
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uint8_t cr;
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uint8_t pr;
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};
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static uint64_t opba_readb(void *opaque, hwaddr addr, unsigned size)
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static uint64_t opba_readb(void *opaque, hwaddr addr, unsigned size)
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{
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{
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ppc4xx_opba_t *opba = opaque;
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Ppc405OpbaState *opba = opaque;
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uint32_t ret;
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uint32_t ret;
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switch (addr) {
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switch (addr) {
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@ -341,7 +334,7 @@ static uint64_t opba_readb(void *opaque, hwaddr addr, unsigned size)
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static void opba_writeb(void *opaque, hwaddr addr, uint64_t value,
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static void opba_writeb(void *opaque, hwaddr addr, uint64_t value,
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unsigned size)
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unsigned size)
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{
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{
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ppc4xx_opba_t *opba = opaque;
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Ppc405OpbaState *opba = opaque;
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trace_opba_writeb(addr, value);
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trace_opba_writeb(addr, value);
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@ -366,25 +359,30 @@ static const MemoryRegionOps opba_ops = {
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.endianness = DEVICE_BIG_ENDIAN,
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.endianness = DEVICE_BIG_ENDIAN,
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};
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};
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static void ppc4xx_opba_reset (void *opaque)
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static void ppc405_opba_reset(DeviceState *dev)
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{
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{
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ppc4xx_opba_t *opba;
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Ppc405OpbaState *opba = PPC405_OPBA(dev);
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opba = opaque;
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opba->cr = 0x00; /* No dynamic priorities - park disabled */
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opba->cr = 0x00; /* No dynamic priorities - park disabled */
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opba->pr = 0x11;
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opba->pr = 0x11;
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}
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}
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static void ppc4xx_opba_init(hwaddr base)
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static void ppc405_opba_realize(DeviceState *dev, Error **errp)
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{
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{
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ppc4xx_opba_t *opba;
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Ppc405OpbaState *s = PPC405_OPBA(dev);
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trace_opba_init(base);
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memory_region_init_io(&s->io, OBJECT(s), &opba_ops, s, "opba", 2);
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sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->io);
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}
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opba = g_new0(ppc4xx_opba_t, 1);
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static void ppc405_opba_class_init(ObjectClass *oc, void *data)
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memory_region_init_io(&opba->io, NULL, &opba_ops, opba, "opba", 0x002);
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{
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memory_region_add_subregion(get_system_memory(), base, &opba->io);
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DeviceClass *dc = DEVICE_CLASS(oc);
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qemu_register_reset(ppc4xx_opba_reset, opba);
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dc->realize = ppc405_opba_realize;
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dc->reset = ppc405_opba_reset;
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/* Reason: only works as function of a ppc4xx SoC */
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dc->user_creatable = false;
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}
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}
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/*****************************************************************************/
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/*****************************************************************************/
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@ -1373,6 +1371,8 @@ static void ppc405_soc_instance_init(Object *obj)
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object_initialize_child(obj, "dma", &s->dma, TYPE_PPC405_DMA);
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object_initialize_child(obj, "dma", &s->dma, TYPE_PPC405_DMA);
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object_initialize_child(obj, "ebc", &s->ebc, TYPE_PPC405_EBC);
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object_initialize_child(obj, "ebc", &s->ebc, TYPE_PPC405_EBC);
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object_initialize_child(obj, "opba", &s->opba, TYPE_PPC405_OPBA);
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}
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}
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static void ppc405_reset(void *opaque)
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static void ppc405_reset(void *opaque)
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@ -1410,7 +1410,11 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
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ppc4xx_pob_init(env);
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ppc4xx_pob_init(env);
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/* OBP arbitrer */
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/* OBP arbitrer */
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ppc4xx_opba_init(0xef600600);
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sbd = SYS_BUS_DEVICE(&s->opba);
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if (!sysbus_realize(sbd, errp)) {
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return;
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}
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sysbus_mmio_map(sbd, 0, 0xef600600);
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/* Universal interrupt controller */
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/* Universal interrupt controller */
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s->uic = qdev_new(TYPE_PPC_UIC);
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s->uic = qdev_new(TYPE_PPC_UIC);
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@ -1523,6 +1527,11 @@ static void ppc405_soc_class_init(ObjectClass *oc, void *data)
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static const TypeInfo ppc405_types[] = {
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static const TypeInfo ppc405_types[] = {
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{
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{
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.name = TYPE_PPC405_OPBA,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(Ppc405OpbaState),
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.class_init = ppc405_opba_class_init,
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}, {
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.name = TYPE_PPC405_EBC,
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.name = TYPE_PPC405_EBC,
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.parent = TYPE_PPC4xx_DCR_DEVICE,
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.parent = TYPE_PPC4xx_DCR_DEVICE,
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.instance_size = sizeof(Ppc405EbcState),
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.instance_size = sizeof(Ppc405EbcState),
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@ -161,7 +161,6 @@ ppc440_pcix_reg_write(uint64_t addr, uint32_t val, uint32_t size) "addr 0x%" PRI
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# ppc405_boards.c
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# ppc405_boards.c
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opba_readb(uint64_t addr, uint32_t val) "addr 0x%" PRIx64 " = 0x%" PRIx32
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opba_readb(uint64_t addr, uint32_t val) "addr 0x%" PRIx64 " = 0x%" PRIx32
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opba_writeb(uint64_t addr, uint64_t val) "addr 0x%" PRIx64 " = 0x%" PRIx64
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opba_writeb(uint64_t addr, uint64_t val) "addr 0x%" PRIx64 " = 0x%" PRIx64
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opba_init(uint64_t addr) "offet 0x%" PRIx64
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ppc405_gpio_read(uint64_t addr, uint32_t size) "addr 0x%" PRIx64 " size %d"
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ppc405_gpio_read(uint64_t addr, uint32_t size) "addr 0x%" PRIx64 " size %d"
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ppc405_gpio_write(uint64_t addr, uint32_t size, uint64_t val) "addr 0x%" PRIx64 " size %d = 0x%" PRIx64
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ppc405_gpio_write(uint64_t addr, uint32_t size, uint64_t val) "addr 0x%" PRIx64 " size %d = 0x%" PRIx64
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