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target/mips: introduce decodetree structure for Cavium Octeon extension 

This patch adds decodetree for Cavium Octeon extension and
an instruction set extension flag for using it in CPU models.

Signed-off-by: Pavel Dovgalyuk <Pavel.Dovgalyuk@ispras.ru>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <165572672162.167724.13656301229517693806.stgit@pasha-ThinkPad-X280>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
This commit is contained in:
Pavel Dovgalyuk 2022-06-20 15:05:21 +03:00 committed by Philippe Mathieu-Daudé
parent 8e3d85d36b
commit 72d680e408
6 changed files with 31 additions and 0 deletions
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1
target/mips/mips-defs.h
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@ -42,6 +42,7 @@
#define INSN_LOONGSON2E 0x0000040000000000ULL #define INSN_LOONGSON2E 0x0000040000000000ULL
#define INSN_LOONGSON2F 0x0000080000000000ULL #define INSN_LOONGSON2F 0x0000080000000000ULL
#define INSN_LOONGSON3A 0x0000100000000000ULL #define INSN_LOONGSON3A 0x0000100000000000ULL
#define INSN_OCTEON 0x0000200000000000ULL
/* /*
* bits 52-63: vendor-specific ASEs * bits 52-63: vendor-specific ASEs
*/ */

2
target/mips/tcg/meson.build
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@ -3,6 +3,7 @@ gen = [
decodetree.process('msa.decode', extra_args: '--decode=decode_ase_msa'), decodetree.process('msa.decode', extra_args: '--decode=decode_ase_msa'),
decodetree.process('tx79.decode', extra_args: '--static-decode=decode_tx79'), decodetree.process('tx79.decode', extra_args: '--static-decode=decode_tx79'),
decodetree.process('vr54xx.decode', extra_args: '--decode=decode_ext_vr54xx'), decodetree.process('vr54xx.decode', extra_args: '--decode=decode_ext_vr54xx'),
decodetree.process('octeon.decode', extra_args: '--decode=decode_ext_octeon'),
] ]
mips_ss.add(gen) mips_ss.add(gen)
@ -24,6 +25,7 @@ mips_ss.add(files(
)) ))
mips_ss.add(when: 'TARGET_MIPS64', if_true: files( mips_ss.add(when: 'TARGET_MIPS64', if_true: files(
'tx79_translate.c', 'tx79_translate.c',
'octeon_translate.c',
), if_false: files( ), if_false: files(
'mxu_translate.c', 'mxu_translate.c',
)) ))

6
target/mips/tcg/octeon.decode Normal file
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@ -0,0 +1,6 @@
# Octeon Architecture Module instruction set
#
# Copyright (C) 2022 Pavel Dovgalyuk
#
# SPDX-License-Identifier: LGPL-2.1-or-later
#

16
target/mips/tcg/octeon_translate.c Normal file
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@ -0,0 +1,16 @@
/*
* Octeon-specific instructions translation routines
*
* Copyright (c) 2022 Pavel Dovgalyuk
*
* SPDX-License-Identifier: GPL-2.0-or-later
*/
#include "qemu/osdep.h"
#include "tcg/tcg-op.h"
#include "tcg/tcg-op-gvec.h"
#include "exec/helper-gen.h"
#include "translate.h"
/* Include the auto-generated decoder. */
#include "decode-octeon.c.inc"

5
target/mips/tcg/translate.c
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@ -15955,6 +15955,11 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
if (cpu_supports_isa(env, INSN_VR54XX) && decode_ext_vr54xx(ctx, ctx->opcode)) { if (cpu_supports_isa(env, INSN_VR54XX) && decode_ext_vr54xx(ctx, ctx->opcode)) {
return; return;
} }
#if defined(TARGET_MIPS64)
if (cpu_supports_isa(env, INSN_OCTEON) && decode_ext_octeon(ctx, ctx->opcode)) {
return;
}
#endif
/* ISA extensions */ /* ISA extensions */
if (ase_msa_available(env) && decode_ase_msa(ctx, ctx->opcode)) { if (ase_msa_available(env) && decode_ase_msa(ctx, ctx->opcode)) {

1
target/mips/tcg/translate.h
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@ -215,6 +215,7 @@ bool decode_ase_msa(DisasContext *ctx, uint32_t insn);
bool decode_ext_txx9(DisasContext *ctx, uint32_t insn); bool decode_ext_txx9(DisasContext *ctx, uint32_t insn);
#if defined(TARGET_MIPS64) #if defined(TARGET_MIPS64)
bool decode_ext_tx79(DisasContext *ctx, uint32_t insn); bool decode_ext_tx79(DisasContext *ctx, uint32_t insn);
bool decode_ext_octeon(DisasContext *ctx, uint32_t insn);
#endif #endif
bool decode_ext_vr54xx(DisasContext *ctx, uint32_t insn); bool decode_ext_vr54xx(DisasContext *ctx, uint32_t insn);