target-microblaze: Convert version_mask to a CPU property
Originally the version_mask PVR bits were manually set for each machine. This is a hassle and difficult to read, instead set them based on the CPU properties. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
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@ -70,7 +70,7 @@ static void machine_cpu_reset(MicroBlazeCPU *cpu)
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env->pvr.regs[10] = 0x0e000000; /* virtex 6 */
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/* setup pvr to match kernel setting */
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env->pvr.regs[0] = (env->pvr.regs[0] & ~PVR0_VERSION_MASK) | (0x14 << 8);
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env->pvr.regs[0] |= (0x14 << 8);
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env->pvr.regs[4] = 0xc56b8000;
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env->pvr.regs[5] = 0xc56be000;
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}
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@ -67,6 +67,7 @@ typedef struct MicroBlazeCPU {
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bool use_mmu;
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bool dcache_writeback;
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bool endi;
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char *version;
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} cfg;
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CPUMBState env;
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@ -26,6 +26,43 @@
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#include "hw/qdev-properties.h"
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#include "migration/vmstate.h"
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static const struct {
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const char *name;
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uint8_t version_id;
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} mb_cpu_lookup[] = {
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/* These key value are as per MBV field in PVR0 */
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{"5.00.a", 0x01},
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{"5.00.b", 0x02},
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{"5.00.c", 0x03},
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{"6.00.a", 0x04},
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{"6.00.b", 0x06},
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{"7.00.a", 0x05},
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{"7.00.b", 0x07},
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{"7.10.a", 0x08},
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{"7.10.b", 0x09},
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{"7.10.c", 0x0a},
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{"7.10.d", 0x0b},
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{"7.20.a", 0x0c},
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{"7.20.b", 0x0d},
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{"7.20.c", 0x0e},
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{"7.20.d", 0x0f},
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{"7.30.a", 0x10},
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{"7.30.b", 0x11},
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{"8.00.a", 0x12},
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{"8.00.b", 0x13},
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{"8.10.a", 0x14},
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{"8.20.a", 0x15},
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{"8.20.b", 0x16},
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{"8.30.a", 0x17},
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{"8.40.a", 0x18},
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{"8.40.b", 0x19},
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{"8.50.a", 0x1A},
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{"9.0", 0x1B},
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{"9.1", 0x1D},
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{"9.2", 0x1F},
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{"9.3", 0x20},
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{NULL, 0},
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};
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static void mb_cpu_set_pc(CPUState *cs, vaddr value)
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{
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@ -88,6 +125,8 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
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MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(dev);
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MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
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CPUMBState *env = &cpu->env;
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uint8_t version_code = 0;
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int i = 0;
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qemu_init_vcpu(cs);
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@ -112,10 +151,22 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
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| PVR2_FPU_EXC_MASK \
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| 0;
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for (i = 0; mb_cpu_lookup[i].name && cpu->cfg.version; i++) {
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if (strcmp(mb_cpu_lookup[i].name, cpu->cfg.version) == 0) {
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version_code = mb_cpu_lookup[i].version_id;
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break;
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}
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}
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if (!version_code) {
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qemu_log("Invalid MicroBlaze version number: %s\n", cpu->cfg.version);
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}
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env->pvr.regs[0] |= (cpu->cfg.stackprot ? PVR0_SPROT_MASK : 0) |
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(cpu->cfg.use_fpu ? PVR0_USE_FPU_MASK : 0) |
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(cpu->cfg.use_mmu ? PVR0_USE_MMU_MASK : 0) |
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(cpu->cfg.endi ? PVR0_ENDI_MASK : 0);
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(cpu->cfg.endi ? PVR0_ENDI_MASK : 0) |
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(version_code << 16);
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env->pvr.regs[2] |= (cpu->cfg.use_fpu ? PVR2_USE_FPU_MASK : 0) |
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(cpu->cfg.use_fpu > 1 ? PVR2_USE_FPU2_MASK : 0);
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@ -176,6 +227,7 @@ static Property mb_properties[] = {
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DEFINE_PROP_BOOL("dcache-writeback", MicroBlazeCPU, cfg.dcache_writeback,
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false),
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DEFINE_PROP_BOOL("endianness", MicroBlazeCPU, cfg.endi, false),
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DEFINE_PROP_STRING("version", MicroBlazeCPU, cfg.version),
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DEFINE_PROP_END_OF_LIST(),
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};
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