target-arm: Add VPIDR_EL2
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1442135278-25281-7-git-send-email-edgar.iglesias@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -385,6 +385,7 @@ typedef struct CPUARMState {
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*/
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*/
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uint64_t c15_ccnt;
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uint64_t c15_ccnt;
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uint64_t pmccfiltr_el0; /* Performance Monitor Filter Register */
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uint64_t pmccfiltr_el0; /* Performance Monitor Filter Register */
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uint64_t vpidr_el2; /* Virtualization Processor ID Register */
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} cp15;
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} cp15;
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struct {
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struct {
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@ -2445,6 +2445,18 @@ static const ARMCPRegInfo strongarm_cp_reginfo[] = {
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REGINFO_SENTINEL
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REGINFO_SENTINEL
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};
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};
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static uint64_t midr_read(CPUARMState *env, const ARMCPRegInfo *ri)
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{
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ARMCPU *cpu = arm_env_get_cpu(env);
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unsigned int cur_el = arm_current_el(env);
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bool secure = arm_is_secure(env);
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if (arm_feature(&cpu->env, ARM_FEATURE_EL2) && !secure && cur_el == 1) {
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return env->cp15.vpidr_el2;
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}
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return raw_read(env, ri);
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}
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static uint64_t mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri)
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static uint64_t mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri)
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{
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{
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ARMCPU *cpu = ARM_CPU(arm_env_get_cpu(env));
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ARMCPU *cpu = ARM_CPU(arm_env_get_cpu(env));
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@ -4121,6 +4133,19 @@ void register_cp_regs_for_features(ARMCPU *cpu)
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define_arm_cp_regs(cpu, v8_cp_reginfo);
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define_arm_cp_regs(cpu, v8_cp_reginfo);
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}
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}
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if (arm_feature(env, ARM_FEATURE_EL2)) {
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if (arm_feature(env, ARM_FEATURE_EL2)) {
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ARMCPRegInfo vpidr_regs[] = {
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{ .name = "VPIDR", .state = ARM_CP_STATE_AA32,
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.cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0,
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.access = PL2_RW, .accessfn = access_el3_aa32ns,
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.resetvalue = cpu->midr,
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.fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) },
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{ .name = "VPIDR_EL2", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0,
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.access = PL2_RW, .resetvalue = cpu->midr,
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.fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) },
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REGINFO_SENTINEL
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};
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define_arm_cp_regs(cpu, vpidr_regs);
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define_arm_cp_regs(cpu, el2_cp_reginfo);
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define_arm_cp_regs(cpu, el2_cp_reginfo);
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/* RVBAR_EL2 is only implemented if EL2 is the highest EL */
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/* RVBAR_EL2 is only implemented if EL2 is the highest EL */
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if (!arm_feature(env, ARM_FEATURE_EL3)) {
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if (!arm_feature(env, ARM_FEATURE_EL3)) {
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@ -4136,6 +4161,18 @@ void register_cp_regs_for_features(ARMCPU *cpu)
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* register the no_el2 reginfos.
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* register the no_el2 reginfos.
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*/
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*/
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if (arm_feature(env, ARM_FEATURE_EL3)) {
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if (arm_feature(env, ARM_FEATURE_EL3)) {
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/* When EL3 exists but not EL2, VPIDR takes the value
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* of MIDR_EL1.
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*/
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ARMCPRegInfo vpidr_regs[] = {
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{ .name = "VPIDR_EL2", .state = ARM_CP_STATE_BOTH,
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.opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0,
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.access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any,
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.type = ARM_CP_CONST, .resetvalue = cpu->midr,
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.fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) },
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REGINFO_SENTINEL
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};
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define_arm_cp_regs(cpu, vpidr_regs);
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define_arm_cp_regs(cpu, el3_no_el2_cp_reginfo);
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define_arm_cp_regs(cpu, el3_no_el2_cp_reginfo);
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}
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}
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}
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}
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@ -4213,6 +4250,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
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.cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = CP_ANY,
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.cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = CP_ANY,
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.access = PL1_R, .resetvalue = cpu->midr,
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.access = PL1_R, .resetvalue = cpu->midr,
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.writefn = arm_cp_write_ignore, .raw_writefn = raw_write,
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.writefn = arm_cp_write_ignore, .raw_writefn = raw_write,
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.readfn = midr_read,
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.fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid),
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.fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid),
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.type = ARM_CP_OVERRIDE },
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.type = ARM_CP_OVERRIDE },
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/* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */
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/* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */
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@ -4236,7 +4274,9 @@ void register_cp_regs_for_features(ARMCPU *cpu)
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ARMCPRegInfo id_v8_midr_cp_reginfo[] = {
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ARMCPRegInfo id_v8_midr_cp_reginfo[] = {
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{ .name = "MIDR_EL1", .state = ARM_CP_STATE_BOTH,
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{ .name = "MIDR_EL1", .state = ARM_CP_STATE_BOTH,
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.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 0,
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.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 0,
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.access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->midr },
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.access = PL1_R, .type = ARM_CP_NO_RAW, .resetvalue = cpu->midr,
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.fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid),
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.readfn = midr_read },
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/* crn = 0 op1 = 0 crm = 0 op2 = 4,7 : AArch32 aliases of MIDR */
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/* crn = 0 op1 = 0 crm = 0 op2 = 4,7 : AArch32 aliases of MIDR */
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{ .name = "MIDR", .type = ARM_CP_ALIAS | ARM_CP_CONST,
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{ .name = "MIDR", .type = ARM_CP_ALIAS | ARM_CP_CONST,
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.cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 4,
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.cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 4,
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