tcg: Replace tcg_abort with g_assert_not_reached

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2023-04-05 12:09:14 -07:00
parent 1a057554cc
commit 732e89f4c4
13 changed files with 47 additions and 55 deletions

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@ -967,12 +967,6 @@ typedef struct TCGTargetOpDef {
const char *args_ct_str[TCG_MAX_OP_ARGS];
} TCGTargetOpDef;
#define tcg_abort() \
do {\
fprintf(stderr, "%s:%d: tcg fatal error\n", __FILE__, __LINE__);\
abort();\
} while (0)
bool tcg_op_supported(TCGOpcode op);
void tcg_gen_callN(void *func, TCGTemp *ret, int nargs, TCGTemp **args);

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@ -476,7 +476,7 @@ static TCGv gen_op_deposit_reg_v(DisasContext *s, MemOp ot, int reg, TCGv dest,
break;
#endif
default:
tcg_abort();
g_assert_not_reached();
}
return cpu_regs[reg];
}
@ -660,7 +660,7 @@ static void gen_lea_v_seg(DisasContext *s, MemOp aflag, TCGv a0,
}
break;
default:
tcg_abort();
g_assert_not_reached();
}
if (ovr_seg >= 0) {
@ -765,7 +765,7 @@ static void gen_helper_in_func(MemOp ot, TCGv v, TCGv_i32 n)
gen_helper_inl(v, cpu_env, n);
break;
default:
tcg_abort();
g_assert_not_reached();
}
}
@ -782,7 +782,7 @@ static void gen_helper_out_func(MemOp ot, TCGv_i32 v, TCGv_i32 n)
gen_helper_outl(cpu_env, v, n);
break;
default:
tcg_abort();
g_assert_not_reached();
}
}
@ -1932,7 +1932,7 @@ static void gen_rotc_rm_T1(DisasContext *s, MemOp ot, int op1,
break;
#endif
default:
tcg_abort();
g_assert_not_reached();
}
} else {
switch (ot) {
@ -1951,7 +1951,7 @@ static void gen_rotc_rm_T1(DisasContext *s, MemOp ot, int op1,
break;
#endif
default:
tcg_abort();
g_assert_not_reached();
}
}
/* store */
@ -2282,7 +2282,7 @@ static AddressParts gen_lea_modrm_0(CPUX86State *env, DisasContext *s,
break;
default:
tcg_abort();
g_assert_not_reached();
}
done:
@ -2434,7 +2434,7 @@ static inline uint32_t insn_get(CPUX86State *env, DisasContext *s, MemOp ot)
ret = x86_ldl_code(env, s);
break;
default:
tcg_abort();
g_assert_not_reached();
}
return ret;
}
@ -3723,7 +3723,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
gen_op_mov_reg_v(s, MO_16, R_EAX, s->T0);
break;
default:
tcg_abort();
g_assert_not_reached();
}
break;
case 0x99: /* CDQ/CWD */
@ -3748,7 +3748,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu)
gen_op_mov_reg_v(s, MO_16, R_EDX, s->T0);
break;
default:
tcg_abort();
g_assert_not_reached();
}
break;
case 0x1af: /* imul Gv, Ev */

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@ -418,7 +418,7 @@ static int get_mem_index(DisasContext *s)
case PSW_ASC_HOME >> FLAG_MASK_PSW_SHIFT:
return MMU_HOME_IDX;
default:
tcg_abort();
g_assert_not_reached();
break;
}
#endif
@ -652,7 +652,7 @@ static void gen_op_calc_cc(DisasContext *s)
gen_helper_calc_cc(cc_op, cpu_env, cc_op, cc_src, cc_dst, cc_vr);
break;
default:
tcg_abort();
g_assert_not_reached();
}
/* We now have cc in cc_op as constant */

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@ -1778,7 +1778,7 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp memop, TCGType ext,
tcg_out_ldst_r(s, I3312_LDRX, data_r, addr_r, otype, off_r);
break;
default:
tcg_abort();
g_assert_not_reached();
}
}
@ -1800,7 +1800,7 @@ static void tcg_out_qemu_st_direct(TCGContext *s, MemOp memop,
tcg_out_ldst_r(s, I3312_STRX, data_r, addr_r, otype, off_r);
break;
default:
tcg_abort();
g_assert_not_reached();
}
}

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@ -2302,7 +2302,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */
case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */
default:
tcg_abort();
g_assert_not_reached();
}
}

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@ -218,7 +218,7 @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
tcg_patch8(code_ptr, value);
break;
default:
tcg_abort();
g_assert_not_reached();
}
return true;
}
@ -1095,7 +1095,7 @@ static inline void tcg_out_pushi(TCGContext *s, tcg_target_long val)
tcg_out_opc(s, OPC_PUSH_Iv, 0, 0, 0);
tcg_out32(s, val);
} else {
tcg_abort();
g_assert_not_reached();
}
}
@ -1359,7 +1359,7 @@ static void tgen_arithi(TCGContext *s, int c, int r0,
return;
}
tcg_abort();
g_assert_not_reached();
}
static void tcg_out_addi(TCGContext *s, int reg, tcg_target_long val)
@ -1523,7 +1523,7 @@ static void tcg_out_brcond2(TCGContext *s, const TCGArg *args,
label_this, small);
break;
default:
tcg_abort();
g_assert_not_reached();
}
tcg_out_label(s, label_next);
}
@ -1958,7 +1958,7 @@ static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
}
break;
default:
tcg_abort();
g_assert_not_reached();
}
/* Jump to the code corresponding to next IR of qemu_st */
@ -2788,7 +2788,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
/* load bits 0..15 */
tcg_out_modrm(s, OPC_MOVL_EvGv | P_DATA16, a2, a0);
} else {
tcg_abort();
g_assert_not_reached();
}
break;
@ -2841,7 +2841,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */
case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */
default:
tcg_abort();
g_assert_not_reached();
}
#undef OP_32_64

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@ -798,7 +798,7 @@ static void tcg_out_setcond(TCGContext *s, TCGCond cond, TCGReg ret,
break;
default:
tcg_abort();
g_assert_not_reached();
break;
}
}
@ -855,7 +855,7 @@ static void tcg_out_brcond(TCGContext *s, TCGCond cond, TCGReg arg1,
break;
default:
tcg_abort();
g_assert_not_reached();
break;
}
@ -1337,7 +1337,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
}
break;
default:
tcg_abort();
g_assert_not_reached();
}
i = tcg_out_call_iarg_imm(s, i, oi);
@ -1527,7 +1527,7 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi,
}
break;
default:
tcg_abort();
g_assert_not_reached();
}
}
@ -1775,7 +1775,7 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg lo, TCGReg hi,
break;
default:
tcg_abort();
g_assert_not_reached();
}
}
@ -1848,7 +1848,7 @@ static void tcg_out_qemu_st_unalign(TCGContext *s, TCGReg lo, TCGReg hi,
break;
default:
tcg_abort();
g_assert_not_reached();
}
}
static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64)
@ -2420,7 +2420,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */
case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */
default:
tcg_abort();
g_assert_not_reached();
}
}

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@ -453,9 +453,7 @@ static uint64_t do_constant_folding_2(TCGOpcode op, uint64_t x, uint64_t y)
return (uint64_t)x % ((uint64_t)y ? : 1);
default:
fprintf(stderr,
"Unrecognized operation %d in do_constant_folding.\n", op);
tcg_abort();
g_assert_not_reached();
}
}
@ -493,7 +491,7 @@ static bool do_constant_folding_cond_32(uint32_t x, uint32_t y, TCGCond c)
case TCG_COND_GTU:
return x > y;
default:
tcg_abort();
g_assert_not_reached();
}
}
@ -521,7 +519,7 @@ static bool do_constant_folding_cond_64(uint64_t x, uint64_t y, TCGCond c)
case TCG_COND_GTU:
return x > y;
default:
tcg_abort();
g_assert_not_reached();
}
}
@ -541,7 +539,7 @@ static bool do_constant_folding_cond_eq(TCGCond c)
case TCG_COND_EQ:
return 1;
default:
tcg_abort();
g_assert_not_reached();
}
}

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@ -1510,7 +1510,7 @@ static void tcg_out_cmp(TCGContext *s, int cond, TCGArg arg1, TCGArg arg2,
break;
default:
tcg_abort();
g_assert_not_reached();
}
op |= BF(cr) | ((type == TCG_TYPE_I64) << 21);
@ -1681,7 +1681,7 @@ static void tcg_out_setcond(TCGContext *s, TCGType type, TCGCond cond,
break;
default:
tcg_abort();
g_assert_not_reached();
}
}
@ -1835,7 +1835,7 @@ static void tcg_out_cmp2(TCGContext *s, const TCGArg *args,
break;
default:
tcg_abort();
g_assert_not_reached();
}
}
@ -3126,7 +3126,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */
case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */
default:
tcg_abort();
g_assert_not_reached();
}
}

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@ -1641,7 +1641,7 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp opc, TCGReg data,
break;
default:
tcg_abort();
g_assert_not_reached();
}
}
@ -1687,7 +1687,7 @@ static void tcg_out_qemu_st_direct(TCGContext *s, MemOp opc, TCGReg data,
break;
default:
tcg_abort();
g_assert_not_reached();
}
}
@ -1818,7 +1818,7 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
tcg_out_mov(s, TCG_TYPE_I64, TCG_REG_R4, data_reg);
break;
default:
tcg_abort();
g_assert_not_reached();
}
tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_R5, oi);
tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R6, (uintptr_t)lb->raddr);
@ -2645,7 +2645,7 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */
case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */
default:
tcg_abort();
g_assert_not_reached();
}
}

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@ -1701,7 +1701,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */
case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */
default:
tcg_abort();
g_assert_not_reached();
}
}

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@ -3680,7 +3680,7 @@ static void temp_sync(TCGContext *s, TCGTemp *ts, TCGRegSet allocated_regs,
case TEMP_VAL_DEAD:
default:
tcg_abort();
g_assert_not_reached();
}
ts->mem_coherent = 1;
}
@ -3767,7 +3767,7 @@ static TCGReg tcg_reg_alloc(TCGContext *s, TCGRegSet required_regs,
}
}
tcg_abort();
g_assert_not_reached();
}
static TCGReg tcg_reg_alloc_pair(TCGContext *s, TCGRegSet required_regs,
@ -3813,7 +3813,7 @@ static TCGReg tcg_reg_alloc_pair(TCGContext *s, TCGRegSet required_regs,
}
}
}
tcg_abort();
g_assert_not_reached();
}
/* Make sure the temporary is in a register. If needed, allocate the register
@ -3860,7 +3860,7 @@ static void temp_load(TCGContext *s, TCGTemp *ts, TCGRegSet desired_regs,
break;
case TEMP_VAL_DEAD:
default:
tcg_abort();
g_assert_not_reached();
}
set_temp_val_reg(s, ts, reg);
}

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@ -796,7 +796,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */
case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */
default:
tcg_abort();
g_assert_not_reached();
}
}