tcg-i386: Tidy softmmu routines
Pass two TCGReg to tcg_out_tlb_load, rather than idx+args. Move ldst_optimization routines just below tcg_out_tlb_load to avoid the need for forward declarations. Use TCGReg enum in preference to int where apprpriate. Signed-off-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Richard Henderson
parent
37c5d0d5d1
commit
7352ee546c
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@ -1043,22 +1043,10 @@ static const void * const qemu_st_helpers[4] = {
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helper_ret_stq_mmu,
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};
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static void add_qemu_ldst_label(TCGContext *s,
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int is_ld,
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int opc,
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int data_reg,
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int data_reg2,
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int addrlo_reg,
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int addrhi_reg,
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int mem_index,
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uint8_t *raddr,
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uint8_t **label_ptr);
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/* Perform the TLB load and compare.
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Inputs:
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ADDRLO_IDX contains the index into ARGS of the low part of the
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address; the high part of the address is at ADDR_LOW_IDX+1.
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ADDRLO and ADDRHI contain the low and high part of the address.
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MEM_INDEX and S_BITS are the memory context and log2 size of the load.
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@ -1076,14 +1064,12 @@ static void add_qemu_ldst_label(TCGContext *s,
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First argument register is clobbered. */
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static inline void tcg_out_tlb_load(TCGContext *s, int addrlo_idx,
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static inline void tcg_out_tlb_load(TCGContext *s, TCGReg addrlo, TCGReg addrhi,
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int mem_index, TCGMemOp s_bits,
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const TCGArg *args,
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uint8_t **label_ptr, int which)
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{
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const int addrlo = args[addrlo_idx];
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const int r0 = TCG_REG_L0;
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const int r1 = TCG_REG_L1;
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const TCGReg r0 = TCG_REG_L0;
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const TCGReg r1 = TCG_REG_L1;
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TCGType ttype = TCG_TYPE_I32;
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TCGType htype = TCG_TYPE_I32;
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int trexw = 0, hrexw = 0;
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@ -1132,7 +1118,7 @@ static inline void tcg_out_tlb_load(TCGContext *s, int addrlo_idx,
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if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) {
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/* cmp 4(r0), addrhi */
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tcg_out_modrm_offset(s, OPC_CMP_GvEv, args[addrlo_idx+1], r0, 4);
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tcg_out_modrm_offset(s, OPC_CMP_GvEv, addrhi, r0, 4);
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/* jne slow_path */
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tcg_out_opc(s, OPC_JCC_long + JCC_JNE, 0, 0, 0);
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@ -1146,320 +1132,25 @@ static inline void tcg_out_tlb_load(TCGContext *s, int addrlo_idx,
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tcg_out_modrm_offset(s, OPC_ADD_GvEv + hrexw, r1, r0,
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offsetof(CPUTLBEntry, addend) - which);
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}
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#elif defined(__x86_64__) && defined(__linux__)
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# include <asm/prctl.h>
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# include <sys/prctl.h>
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int arch_prctl(int code, unsigned long addr);
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static int guest_base_flags;
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static inline void setup_guest_base_seg(void)
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{
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if (arch_prctl(ARCH_SET_GS, GUEST_BASE) == 0) {
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guest_base_flags = P_GS;
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}
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}
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#else
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# define guest_base_flags 0
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static inline void setup_guest_base_seg(void) { }
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#endif /* SOFTMMU */
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static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg datalo, TCGReg datahi,
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TCGReg base, intptr_t ofs, int seg,
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TCGMemOp memop)
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{
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const TCGMemOp bswap = memop & MO_BSWAP;
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switch (memop & MO_SSIZE) {
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case MO_UB:
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tcg_out_modrm_offset(s, OPC_MOVZBL + seg, datalo, base, ofs);
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break;
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case MO_SB:
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tcg_out_modrm_offset(s, OPC_MOVSBL + P_REXW + seg, datalo, base, ofs);
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break;
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case MO_UW:
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tcg_out_modrm_offset(s, OPC_MOVZWL + seg, datalo, base, ofs);
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if (bswap) {
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tcg_out_rolw_8(s, datalo);
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}
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break;
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case MO_SW:
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if (bswap) {
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tcg_out_modrm_offset(s, OPC_MOVZWL + seg, datalo, base, ofs);
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tcg_out_rolw_8(s, datalo);
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tcg_out_modrm(s, OPC_MOVSWL + P_REXW, datalo, datalo);
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} else {
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tcg_out_modrm_offset(s, OPC_MOVSWL + P_REXW + seg,
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datalo, base, ofs);
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}
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break;
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case MO_UL:
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tcg_out_modrm_offset(s, OPC_MOVL_GvEv + seg, datalo, base, ofs);
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if (bswap) {
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tcg_out_bswap32(s, datalo);
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}
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break;
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#if TCG_TARGET_REG_BITS == 64
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case MO_SL:
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if (bswap) {
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tcg_out_modrm_offset(s, OPC_MOVL_GvEv + seg, datalo, base, ofs);
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tcg_out_bswap32(s, datalo);
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tcg_out_ext32s(s, datalo, datalo);
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} else {
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tcg_out_modrm_offset(s, OPC_MOVSLQ + seg, datalo, base, ofs);
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}
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break;
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#endif
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case MO_Q:
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if (TCG_TARGET_REG_BITS == 64) {
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tcg_out_modrm_offset(s, OPC_MOVL_GvEv + P_REXW + seg,
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datalo, base, ofs);
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if (bswap) {
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tcg_out_bswap64(s, datalo);
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}
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} else {
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if (bswap) {
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int t = datalo;
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datalo = datahi;
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datahi = t;
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}
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if (base != datalo) {
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tcg_out_modrm_offset(s, OPC_MOVL_GvEv + seg,
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datalo, base, ofs);
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tcg_out_modrm_offset(s, OPC_MOVL_GvEv + seg,
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datahi, base, ofs + 4);
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} else {
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tcg_out_modrm_offset(s, OPC_MOVL_GvEv + seg,
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datahi, base, ofs + 4);
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tcg_out_modrm_offset(s, OPC_MOVL_GvEv + seg,
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datalo, base, ofs);
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}
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if (bswap) {
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tcg_out_bswap32(s, datalo);
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tcg_out_bswap32(s, datahi);
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}
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}
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break;
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default:
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tcg_abort();
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}
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}
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/* XXX: qemu_ld and qemu_st could be modified to clobber only EDX and
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EAX. It will be useful once fixed registers globals are less
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common. */
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static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, TCGMemOp opc)
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{
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int data_reg, data_reg2 = 0;
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int addrlo_idx;
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#if defined(CONFIG_SOFTMMU)
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int mem_index;
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TCGMemOp s_bits;
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uint8_t *label_ptr[2];
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#endif
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data_reg = args[0];
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addrlo_idx = 1;
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if (TCG_TARGET_REG_BITS == 32 && (opc & MO_SIZE) == MO_64) {
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data_reg2 = args[1];
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addrlo_idx = 2;
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}
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#if defined(CONFIG_SOFTMMU)
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mem_index = args[addrlo_idx + 1 + (TARGET_LONG_BITS > TCG_TARGET_REG_BITS)];
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s_bits = opc & MO_SIZE;
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tcg_out_tlb_load(s, addrlo_idx, mem_index, s_bits, args,
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label_ptr, offsetof(CPUTLBEntry, addr_read));
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/* TLB Hit. */
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tcg_out_qemu_ld_direct(s, data_reg, data_reg2, TCG_REG_L1, 0, 0, opc);
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/* Record the current context of a load into ldst label */
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add_qemu_ldst_label(s,
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1,
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opc,
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data_reg,
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data_reg2,
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args[addrlo_idx],
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args[addrlo_idx + 1],
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mem_index,
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s->code_ptr,
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label_ptr);
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#else
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{
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int32_t offset = GUEST_BASE;
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int base = args[addrlo_idx];
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int seg = 0;
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/* ??? We assume all operations have left us with register contents
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that are zero extended. So far this appears to be true. If we
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want to enforce this, we can either do an explicit zero-extension
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here, or (if GUEST_BASE == 0, or a segment register is in use)
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use the ADDR32 prefix. For now, do nothing. */
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if (GUEST_BASE && guest_base_flags) {
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seg = guest_base_flags;
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offset = 0;
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} else if (TCG_TARGET_REG_BITS == 64 && offset != GUEST_BASE) {
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tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_L1, GUEST_BASE);
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tgen_arithr(s, ARITH_ADD + P_REXW, TCG_REG_L1, base);
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base = TCG_REG_L1;
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offset = 0;
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}
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tcg_out_qemu_ld_direct(s, data_reg, data_reg2, base, offset, seg, opc);
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}
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#endif
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}
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static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg datalo, TCGReg datahi,
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TCGReg base, intptr_t ofs, int seg,
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TCGMemOp memop)
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{
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const TCGMemOp bswap = memop & MO_BSWAP;
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/* ??? Ideally we wouldn't need a scratch register. For user-only,
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we could perform the bswap twice to restore the original value
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instead of moving to the scratch. But as it is, the L constraint
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means that TCG_REG_L0 is definitely free here. */
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const TCGReg scratch = TCG_REG_L0;
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switch (memop & MO_SIZE) {
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case MO_8:
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tcg_out_modrm_offset(s, OPC_MOVB_EvGv + P_REXB_R + seg,
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datalo, base, ofs);
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break;
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case MO_16:
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if (bswap) {
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tcg_out_mov(s, TCG_TYPE_I32, scratch, datalo);
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tcg_out_rolw_8(s, scratch);
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datalo = scratch;
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}
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tcg_out_modrm_offset(s, OPC_MOVL_EvGv + P_DATA16 + seg,
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datalo, base, ofs);
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break;
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case MO_32:
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if (bswap) {
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tcg_out_mov(s, TCG_TYPE_I32, scratch, datalo);
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tcg_out_bswap32(s, scratch);
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datalo = scratch;
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}
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tcg_out_modrm_offset(s, OPC_MOVL_EvGv + seg, datalo, base, ofs);
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break;
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case MO_64:
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if (TCG_TARGET_REG_BITS == 64) {
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if (bswap) {
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tcg_out_mov(s, TCG_TYPE_I64, scratch, datalo);
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tcg_out_bswap64(s, scratch);
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datalo = scratch;
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}
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tcg_out_modrm_offset(s, OPC_MOVL_EvGv + P_REXW + seg,
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datalo, base, ofs);
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} else if (bswap) {
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tcg_out_mov(s, TCG_TYPE_I32, scratch, datahi);
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tcg_out_bswap32(s, scratch);
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tcg_out_modrm_offset(s, OPC_MOVL_EvGv + seg, scratch, base, ofs);
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tcg_out_mov(s, TCG_TYPE_I32, scratch, datalo);
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tcg_out_bswap32(s, scratch);
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tcg_out_modrm_offset(s, OPC_MOVL_EvGv + seg, scratch, base, ofs+4);
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} else {
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tcg_out_modrm_offset(s, OPC_MOVL_EvGv + seg, datalo, base, ofs);
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tcg_out_modrm_offset(s, OPC_MOVL_EvGv + seg, datahi, base, ofs+4);
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}
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break;
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default:
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tcg_abort();
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}
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}
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static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, TCGMemOp opc)
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{
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int data_reg, data_reg2 = 0;
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int addrlo_idx;
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#if defined(CONFIG_SOFTMMU)
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int mem_index;
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TCGMemOp s_bits;
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uint8_t *label_ptr[2];
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#endif
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data_reg = args[0];
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addrlo_idx = 1;
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if (TCG_TARGET_REG_BITS == 32 && opc == 3) {
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data_reg2 = args[1];
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addrlo_idx = 2;
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}
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#if defined(CONFIG_SOFTMMU)
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mem_index = args[addrlo_idx + 1 + (TARGET_LONG_BITS > TCG_TARGET_REG_BITS)];
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s_bits = opc & MO_SIZE;
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tcg_out_tlb_load(s, addrlo_idx, mem_index, s_bits, args,
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label_ptr, offsetof(CPUTLBEntry, addr_write));
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/* TLB Hit. */
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tcg_out_qemu_st_direct(s, data_reg, data_reg2, TCG_REG_L1, 0, 0, opc);
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/* Record the current context of a store into ldst label */
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add_qemu_ldst_label(s,
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0,
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opc,
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data_reg,
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data_reg2,
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args[addrlo_idx],
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args[addrlo_idx + 1],
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mem_index,
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s->code_ptr,
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label_ptr);
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#else
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{
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int32_t offset = GUEST_BASE;
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int base = args[addrlo_idx];
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int seg = 0;
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/* ??? We assume all operations have left us with register contents
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that are zero extended. So far this appears to be true. If we
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want to enforce this, we can either do an explicit zero-extension
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here, or (if GUEST_BASE == 0, or a segment register is in use)
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use the ADDR32 prefix. For now, do nothing. */
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if (GUEST_BASE && guest_base_flags) {
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seg = guest_base_flags;
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offset = 0;
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} else if (TCG_TARGET_REG_BITS == 64 && offset != GUEST_BASE) {
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tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_L1, GUEST_BASE);
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tgen_arithr(s, ARITH_ADD + P_REXW, TCG_REG_L1, base);
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base = TCG_REG_L1;
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offset = 0;
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}
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tcg_out_qemu_st_direct(s, data_reg, data_reg2, base, offset, seg, opc);
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}
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#endif
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}
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#if defined(CONFIG_SOFTMMU)
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/*
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* Record the context of a call to the out of line helper code for the slow path
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* for a load or store, so that we can later generate the correct helper code
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*/
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static void add_qemu_ldst_label(TCGContext *s,
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int is_ld,
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int opc,
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int data_reg,
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int data_reg2,
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int addrlo_reg,
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int addrhi_reg,
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int mem_index,
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uint8_t *raddr,
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static void add_qemu_ldst_label(TCGContext *s, int is_ld, TCGMemOp opc,
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TCGReg datalo, TCGReg datahi,
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TCGReg addrlo, TCGReg addrhi,
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int mem_index, uint8_t *raddr,
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uint8_t **label_ptr)
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{
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TCGLabelQemuLdst *label = new_ldst_label(s);
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label->is_ld = is_ld;
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label->opc = opc;
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label->datalo_reg = data_reg;
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label->datahi_reg = data_reg2;
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label->addrlo_reg = addrlo_reg;
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label->addrhi_reg = addrhi_reg;
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label->datalo_reg = datalo;
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label->datahi_reg = datahi;
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label->addrlo_reg = addrlo;
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label->addrhi_reg = addrhi;
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label->mem_index = mem_index;
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label->raddr = raddr;
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label->label_ptr[0] = label_ptr[0];
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@ -1618,7 +1309,275 @@ static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
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tcg_out_push(s, retaddr);
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tcg_out_jmp(s, (uintptr_t)qemu_st_helpers[s_bits]);
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}
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#endif /* CONFIG_SOFTMMU */
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#elif defined(__x86_64__) && defined(__linux__)
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# include <asm/prctl.h>
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# include <sys/prctl.h>
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int arch_prctl(int code, unsigned long addr);
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static int guest_base_flags;
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static inline void setup_guest_base_seg(void)
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{
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if (arch_prctl(ARCH_SET_GS, GUEST_BASE) == 0) {
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guest_base_flags = P_GS;
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}
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}
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#else
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# define guest_base_flags 0
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static inline void setup_guest_base_seg(void) { }
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#endif /* SOFTMMU */
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static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg datalo, TCGReg datahi,
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TCGReg base, intptr_t ofs, int seg,
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TCGMemOp memop)
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{
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const TCGMemOp bswap = memop & MO_BSWAP;
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switch (memop & MO_SSIZE) {
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case MO_UB:
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tcg_out_modrm_offset(s, OPC_MOVZBL + seg, datalo, base, ofs);
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break;
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case MO_SB:
|
||||
tcg_out_modrm_offset(s, OPC_MOVSBL + P_REXW + seg, datalo, base, ofs);
|
||||
break;
|
||||
case MO_UW:
|
||||
tcg_out_modrm_offset(s, OPC_MOVZWL + seg, datalo, base, ofs);
|
||||
if (bswap) {
|
||||
tcg_out_rolw_8(s, datalo);
|
||||
}
|
||||
break;
|
||||
case MO_SW:
|
||||
if (bswap) {
|
||||
tcg_out_modrm_offset(s, OPC_MOVZWL + seg, datalo, base, ofs);
|
||||
tcg_out_rolw_8(s, datalo);
|
||||
tcg_out_modrm(s, OPC_MOVSWL + P_REXW, datalo, datalo);
|
||||
} else {
|
||||
tcg_out_modrm_offset(s, OPC_MOVSWL + P_REXW + seg,
|
||||
datalo, base, ofs);
|
||||
}
|
||||
break;
|
||||
case MO_UL:
|
||||
tcg_out_modrm_offset(s, OPC_MOVL_GvEv + seg, datalo, base, ofs);
|
||||
if (bswap) {
|
||||
tcg_out_bswap32(s, datalo);
|
||||
}
|
||||
break;
|
||||
#if TCG_TARGET_REG_BITS == 64
|
||||
case MO_SL:
|
||||
if (bswap) {
|
||||
tcg_out_modrm_offset(s, OPC_MOVL_GvEv + seg, datalo, base, ofs);
|
||||
tcg_out_bswap32(s, datalo);
|
||||
tcg_out_ext32s(s, datalo, datalo);
|
||||
} else {
|
||||
tcg_out_modrm_offset(s, OPC_MOVSLQ + seg, datalo, base, ofs);
|
||||
}
|
||||
break;
|
||||
#endif
|
||||
case MO_Q:
|
||||
if (TCG_TARGET_REG_BITS == 64) {
|
||||
tcg_out_modrm_offset(s, OPC_MOVL_GvEv + P_REXW + seg,
|
||||
datalo, base, ofs);
|
||||
if (bswap) {
|
||||
tcg_out_bswap64(s, datalo);
|
||||
}
|
||||
} else {
|
||||
if (bswap) {
|
||||
int t = datalo;
|
||||
datalo = datahi;
|
||||
datahi = t;
|
||||
}
|
||||
if (base != datalo) {
|
||||
tcg_out_modrm_offset(s, OPC_MOVL_GvEv + seg,
|
||||
datalo, base, ofs);
|
||||
tcg_out_modrm_offset(s, OPC_MOVL_GvEv + seg,
|
||||
datahi, base, ofs + 4);
|
||||
} else {
|
||||
tcg_out_modrm_offset(s, OPC_MOVL_GvEv + seg,
|
||||
datahi, base, ofs + 4);
|
||||
tcg_out_modrm_offset(s, OPC_MOVL_GvEv + seg,
|
||||
datalo, base, ofs);
|
||||
}
|
||||
if (bswap) {
|
||||
tcg_out_bswap32(s, datalo);
|
||||
tcg_out_bswap32(s, datahi);
|
||||
}
|
||||
}
|
||||
break;
|
||||
default:
|
||||
tcg_abort();
|
||||
}
|
||||
}
|
||||
|
||||
/* XXX: qemu_ld and qemu_st could be modified to clobber only EDX and
|
||||
EAX. It will be useful once fixed registers globals are less
|
||||
common. */
|
||||
static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, TCGMemOp opc)
|
||||
{
|
||||
TCGReg datalo, datahi, addrlo;
|
||||
#if defined(CONFIG_SOFTMMU)
|
||||
TCGReg addrhi;
|
||||
int mem_index;
|
||||
TCGMemOp s_bits;
|
||||
uint8_t *label_ptr[2];
|
||||
#endif
|
||||
|
||||
datalo = *args++;
|
||||
datahi = (TCG_TARGET_REG_BITS == 32 && opc == 3 ? *args++ : 0);
|
||||
addrlo = *args++;
|
||||
|
||||
#if defined(CONFIG_SOFTMMU)
|
||||
addrhi = (TARGET_LONG_BITS > TCG_TARGET_REG_BITS ? *args++ : 0);
|
||||
mem_index = *args++;
|
||||
s_bits = opc & MO_SIZE;
|
||||
|
||||
tcg_out_tlb_load(s, addrlo, addrhi, mem_index, s_bits,
|
||||
label_ptr, offsetof(CPUTLBEntry, addr_read));
|
||||
|
||||
/* TLB Hit. */
|
||||
tcg_out_qemu_ld_direct(s, datalo, datahi, TCG_REG_L1, 0, 0, opc);
|
||||
|
||||
/* Record the current context of a load into ldst label */
|
||||
add_qemu_ldst_label(s, 1, opc, datalo, datahi, addrlo, addrhi,
|
||||
mem_index, s->code_ptr, label_ptr);
|
||||
#else
|
||||
{
|
||||
int32_t offset = GUEST_BASE;
|
||||
TCGReg base = addrlo;
|
||||
int seg = 0;
|
||||
|
||||
/* ??? We assume all operations have left us with register contents
|
||||
that are zero extended. So far this appears to be true. If we
|
||||
want to enforce this, we can either do an explicit zero-extension
|
||||
here, or (if GUEST_BASE == 0, or a segment register is in use)
|
||||
use the ADDR32 prefix. For now, do nothing. */
|
||||
if (GUEST_BASE && guest_base_flags) {
|
||||
seg = guest_base_flags;
|
||||
offset = 0;
|
||||
} else if (TCG_TARGET_REG_BITS == 64 && offset != GUEST_BASE) {
|
||||
tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_L1, GUEST_BASE);
|
||||
tgen_arithr(s, ARITH_ADD + P_REXW, TCG_REG_L1, base);
|
||||
base = TCG_REG_L1;
|
||||
offset = 0;
|
||||
}
|
||||
|
||||
tcg_out_qemu_ld_direct(s, datalo, datahi, base, offset, seg, opc);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg datalo, TCGReg datahi,
|
||||
TCGReg base, intptr_t ofs, int seg,
|
||||
TCGMemOp memop)
|
||||
{
|
||||
const TCGMemOp bswap = memop & MO_BSWAP;
|
||||
|
||||
/* ??? Ideally we wouldn't need a scratch register. For user-only,
|
||||
we could perform the bswap twice to restore the original value
|
||||
instead of moving to the scratch. But as it is, the L constraint
|
||||
means that TCG_REG_L0 is definitely free here. */
|
||||
const TCGReg scratch = TCG_REG_L0;
|
||||
|
||||
switch (memop & MO_SIZE) {
|
||||
case MO_8:
|
||||
tcg_out_modrm_offset(s, OPC_MOVB_EvGv + P_REXB_R + seg,
|
||||
datalo, base, ofs);
|
||||
break;
|
||||
case MO_16:
|
||||
if (bswap) {
|
||||
tcg_out_mov(s, TCG_TYPE_I32, scratch, datalo);
|
||||
tcg_out_rolw_8(s, scratch);
|
||||
datalo = scratch;
|
||||
}
|
||||
tcg_out_modrm_offset(s, OPC_MOVL_EvGv + P_DATA16 + seg,
|
||||
datalo, base, ofs);
|
||||
break;
|
||||
case MO_32:
|
||||
if (bswap) {
|
||||
tcg_out_mov(s, TCG_TYPE_I32, scratch, datalo);
|
||||
tcg_out_bswap32(s, scratch);
|
||||
datalo = scratch;
|
||||
}
|
||||
tcg_out_modrm_offset(s, OPC_MOVL_EvGv + seg, datalo, base, ofs);
|
||||
break;
|
||||
case MO_64:
|
||||
if (TCG_TARGET_REG_BITS == 64) {
|
||||
if (bswap) {
|
||||
tcg_out_mov(s, TCG_TYPE_I64, scratch, datalo);
|
||||
tcg_out_bswap64(s, scratch);
|
||||
datalo = scratch;
|
||||
}
|
||||
tcg_out_modrm_offset(s, OPC_MOVL_EvGv + P_REXW + seg,
|
||||
datalo, base, ofs);
|
||||
} else if (bswap) {
|
||||
tcg_out_mov(s, TCG_TYPE_I32, scratch, datahi);
|
||||
tcg_out_bswap32(s, scratch);
|
||||
tcg_out_modrm_offset(s, OPC_MOVL_EvGv + seg, scratch, base, ofs);
|
||||
tcg_out_mov(s, TCG_TYPE_I32, scratch, datalo);
|
||||
tcg_out_bswap32(s, scratch);
|
||||
tcg_out_modrm_offset(s, OPC_MOVL_EvGv + seg, scratch, base, ofs+4);
|
||||
} else {
|
||||
tcg_out_modrm_offset(s, OPC_MOVL_EvGv + seg, datalo, base, ofs);
|
||||
tcg_out_modrm_offset(s, OPC_MOVL_EvGv + seg, datahi, base, ofs+4);
|
||||
}
|
||||
break;
|
||||
default:
|
||||
tcg_abort();
|
||||
}
|
||||
}
|
||||
|
||||
static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, TCGMemOp opc)
|
||||
{
|
||||
TCGReg datalo, datahi, addrlo;
|
||||
#if defined(CONFIG_SOFTMMU)
|
||||
TCGReg addrhi;
|
||||
int mem_index;
|
||||
TCGMemOp s_bits;
|
||||
uint8_t *label_ptr[2];
|
||||
#endif
|
||||
|
||||
datalo = *args++;
|
||||
datahi = (TCG_TARGET_REG_BITS == 32 && opc == 3 ? *args++ : 0);
|
||||
addrlo = *args++;
|
||||
|
||||
#if defined(CONFIG_SOFTMMU)
|
||||
addrhi = (TARGET_LONG_BITS > TCG_TARGET_REG_BITS ? *args++ : 0);
|
||||
mem_index = *args++;
|
||||
s_bits = opc & MO_SIZE;
|
||||
|
||||
tcg_out_tlb_load(s, addrlo, addrhi, mem_index, s_bits,
|
||||
label_ptr, offsetof(CPUTLBEntry, addr_write));
|
||||
|
||||
/* TLB Hit. */
|
||||
tcg_out_qemu_st_direct(s, datalo, datahi, TCG_REG_L1, 0, 0, opc);
|
||||
|
||||
/* Record the current context of a store into ldst label */
|
||||
add_qemu_ldst_label(s, 0, opc, datalo, datahi, addrlo, addrhi,
|
||||
mem_index, s->code_ptr, label_ptr);
|
||||
#else
|
||||
{
|
||||
int32_t offset = GUEST_BASE;
|
||||
TCGReg base = addrlo;
|
||||
int seg = 0;
|
||||
|
||||
/* ??? We assume all operations have left us with register contents
|
||||
that are zero extended. So far this appears to be true. If we
|
||||
want to enforce this, we can either do an explicit zero-extension
|
||||
here, or (if GUEST_BASE == 0, or a segment register is in use)
|
||||
use the ADDR32 prefix. For now, do nothing. */
|
||||
if (GUEST_BASE && guest_base_flags) {
|
||||
seg = guest_base_flags;
|
||||
offset = 0;
|
||||
} else if (TCG_TARGET_REG_BITS == 64 && offset != GUEST_BASE) {
|
||||
tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_L1, GUEST_BASE);
|
||||
tgen_arithr(s, ARITH_ADD + P_REXW, TCG_REG_L1, base);
|
||||
base = TCG_REG_L1;
|
||||
offset = 0;
|
||||
}
|
||||
|
||||
tcg_out_qemu_st_direct(s, datalo, datahi, base, offset, seg, opc);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
|
||||
const TCGArg *args, const int *const_args)
|
||||
|
|
|
|||
Loading…
Reference in New Issue