target-alpha: Fix fbcond branch offset.
The instructions use a disp21 like all other branch insns, not the disp16 that was being passed. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
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@ -314,8 +314,7 @@ static inline void gen_bcond(DisasContext *ctx, TCGCond cond, int ra,
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gen_set_label(l2);
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}
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static inline void gen_fbcond(DisasContext *ctx, int opc, int ra,
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int32_t disp16)
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static inline void gen_fbcond(DisasContext *ctx, int opc, int ra, int32_t disp)
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{
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int l1, l2;
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TCGv tmp;
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@ -356,7 +355,7 @@ static inline void gen_fbcond(DisasContext *ctx, int opc, int ra,
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tcg_gen_movi_i64(cpu_pc, ctx->pc);
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tcg_gen_br(l2);
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gen_set_label(l1);
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tcg_gen_movi_i64(cpu_pc, ctx->pc + (int64_t)(disp16 << 2));
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tcg_gen_movi_i64(cpu_pc, ctx->pc + (int64_t)(disp << 2));
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gen_set_label(l2);
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}
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@ -2335,7 +2334,7 @@ static inline int translate_one(DisasContext *ctx, uint32_t insn)
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case 0x31: /* FBEQ */
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case 0x32: /* FBLT */
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case 0x33: /* FBLE */
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gen_fbcond(ctx, opc, ra, disp16);
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gen_fbcond(ctx, opc, ra, disp21);
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ret = 1;
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break;
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case 0x34:
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@ -2348,7 +2347,7 @@ static inline int translate_one(DisasContext *ctx, uint32_t insn)
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case 0x35: /* FBNE */
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case 0x36: /* FBGE */
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case 0x37: /* FBGT */
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gen_fbcond(ctx, opc, ra, disp16);
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gen_fbcond(ctx, opc, ra, disp21);
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ret = 1;
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break;
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case 0x38:
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