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Restore 32-bit I/O accesses on AMD flashes 

(precautionary revert).
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Merge remote-tracking branch 'remotes/philmd-gitlab/tags/pflash-next-20190709' into staging

Restore 32-bit I/O accesses on AMD flashes
(precautionary revert).

# gpg: Signature made Tue 09 Jul 2019 16:18:10 BST
# gpg:                using RSA key E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full]
# Primary key fingerprint: FAAB E75E 1291 7221 DCFD  6BB2 E3E3 2C2C DEAD C0DE

* remotes/philmd-gitlab/tags/pflash-next-20190709:
  Revert "hw/block/pflash_cfi02: Reduce I/O accesses to 16-bit"

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2019-07-09 16:41:48 +01:00
parent 8d358a5ea0 51500d3770
commit 7372849f5b
1 changed files with 4 additions and 1 deletions
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5
hw/block/pflash_cfi02.c
View File

@ -317,6 +317,8 @@ static uint64_t pflash_read(void *opaque, hwaddr offset, unsigned int width)
boff = offset & 0xFF;
if (pfl->width == 2) {
boff = boff >> 1;
} else if (pfl->width == 4) {
boff = boff >> 2;
}
switch (pfl->cmd) {
default:
@ -447,6 +449,8 @@ static void pflash_write(void *opaque, hwaddr offset, uint64_t value,
boff = offset;
if (pfl->width == 2) {
boff = boff >> 1;
} else if (pfl->width == 4) {
boff = boff >> 2;
}
/* Only the least-significant 11 bits are used in most cases. */
boff &= 0x7FF;
@ -706,7 +710,6 @@ static void pflash_write(void *opaque, hwaddr offset, uint64_t value,
static const MemoryRegionOps pflash_cfi02_ops = {
.read = pflash_read,
.write = pflash_write,
.impl.max_access_size = 2,
.valid.min_access_size = 1,
.valid.max_access_size = 4,
.endianness = DEVICE_NATIVE_ENDIAN,