target-sh4: Don't overuse CPUState
Scripted conversion: sed -i "s/CPUState/CPUSH4State/g" target-sh4/*.[hc] sed -i "s/#define CPUSH4State/#define CPUState/" target-sh4/cpu.h Signed-off-by: Andreas Färber <afaerber@suse.de> Acked-by: Anthony Liguori <aliguori@us.ibm.com>
This commit is contained in:
Andreas Färber
parent
a4e3ad19d2
commit
73e5716c89
@ -240,13 +240,13 @@ void cpu_load_tlb(CPUSH4State * env);
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#define MMU_MODE0_SUFFIX _kernel
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#define MMU_MODE1_SUFFIX _user
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#define MMU_USER_IDX 1
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static inline int cpu_mmu_index (CPUState *env)
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static inline int cpu_mmu_index (CPUSH4State *env)
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{
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return (env->sr & SR_MD) == 0 ? 1 : 0;
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}
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#if defined(CONFIG_USER_ONLY)
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static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
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static inline void cpu_clone_regs(CPUSH4State *env, target_ulong newsp)
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{
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if (newsp)
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env->gregs[15] = newsp;
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@ -348,7 +348,7 @@ static inline int cpu_ptel_pr (uint32_t ptel)
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#define TB_FLAG_PENDING_MOVCA (1 << 4)
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static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
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static inline void cpu_get_tb_cpu_state(CPUSH4State *env, target_ulong *pc,
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target_ulong *cs_base, int *flags)
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{
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*pc = env->pc;
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@ -361,14 +361,14 @@ static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
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| (env->movcal_backup ? TB_FLAG_PENDING_MOVCA : 0); /* Bit 4 */
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}
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static inline bool cpu_has_work(CPUState *env)
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static inline bool cpu_has_work(CPUSH4State *env)
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{
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return env->interrupt_request & CPU_INTERRUPT_HARD;
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}
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#include "exec-all.h"
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static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
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static inline void cpu_pc_from_tb(CPUSH4State *env, TranslationBlock *tb)
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{
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env->pc = tb->pc;
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env->flags = tb->flags;
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@ -31,12 +31,12 @@
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#if defined(CONFIG_USER_ONLY)
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void do_interrupt (CPUState *env)
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void do_interrupt (CPUSH4State *env)
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{
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env->exception_index = -1;
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}
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int cpu_sh4_handle_mmu_fault(CPUState * env, target_ulong address, int rw,
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int cpu_sh4_handle_mmu_fault(CPUSH4State * env, target_ulong address, int rw,
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int mmu_idx)
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{
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env->tea = address;
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@ -78,7 +78,7 @@ int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr)
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#define MMU_DADDR_ERROR_READ (-12)
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#define MMU_DADDR_ERROR_WRITE (-13)
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void do_interrupt(CPUState * env)
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void do_interrupt(CPUSH4State * env)
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{
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int do_irq = env->interrupt_request & CPU_INTERRUPT_HARD;
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int do_exp, irq_vector = env->exception_index;
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@ -202,7 +202,7 @@ void do_interrupt(CPUState * env)
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}
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}
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static void update_itlb_use(CPUState * env, int itlbnb)
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static void update_itlb_use(CPUSH4State * env, int itlbnb)
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{
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uint8_t or_mask = 0, and_mask = (uint8_t) - 1;
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@ -227,7 +227,7 @@ static void update_itlb_use(CPUState * env, int itlbnb)
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env->mmucr |= (or_mask << 24);
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}
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static int itlb_replacement(CPUState * env)
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static int itlb_replacement(CPUSH4State * env)
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{
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if ((env->mmucr & 0xe0000000) == 0xe0000000)
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return 0;
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@ -243,7 +243,7 @@ static int itlb_replacement(CPUState * env)
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/* Find the corresponding entry in the right TLB
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Return entry, MMU_DTLB_MISS or MMU_DTLB_MULTIPLE
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*/
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static int find_tlb_entry(CPUState * env, target_ulong address,
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static int find_tlb_entry(CPUSH4State * env, target_ulong address,
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tlb_t * entries, uint8_t nbtlb, int use_asid)
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{
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int match = MMU_DTLB_MISS;
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@ -269,7 +269,7 @@ static int find_tlb_entry(CPUState * env, target_ulong address,
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return match;
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}
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static void increment_urc(CPUState * env)
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static void increment_urc(CPUSH4State * env)
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{
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uint8_t urb, urc;
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@ -285,7 +285,7 @@ static void increment_urc(CPUState * env)
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/* Copy and utlb entry into itlb
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Return entry
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*/
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static int copy_utlb_entry_itlb(CPUState *env, int utlb)
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static int copy_utlb_entry_itlb(CPUSH4State *env, int utlb)
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{
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int itlb;
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@ -303,7 +303,7 @@ static int copy_utlb_entry_itlb(CPUState *env, int utlb)
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/* Find itlb entry
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Return entry, MMU_ITLB_MISS, MMU_ITLB_MULTIPLE or MMU_DTLB_MULTIPLE
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*/
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static int find_itlb_entry(CPUState * env, target_ulong address,
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static int find_itlb_entry(CPUSH4State * env, target_ulong address,
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int use_asid)
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{
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int e;
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@ -321,7 +321,7 @@ static int find_itlb_entry(CPUState * env, target_ulong address,
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/* Find utlb entry
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Return entry, MMU_DTLB_MISS, MMU_DTLB_MULTIPLE */
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static int find_utlb_entry(CPUState * env, target_ulong address, int use_asid)
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static int find_utlb_entry(CPUSH4State * env, target_ulong address, int use_asid)
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{
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/* per utlb access */
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increment_urc(env);
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@ -337,7 +337,7 @@ static int find_utlb_entry(CPUState * env, target_ulong address, int use_asid)
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MMU_ITLB_MULTIPLE, MMU_ITLB_VIOLATION,
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MMU_IADDR_ERROR, MMU_DADDR_ERROR_READ, MMU_DADDR_ERROR_WRITE.
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*/
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static int get_mmu_address(CPUState * env, target_ulong * physical,
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static int get_mmu_address(CPUSH4State * env, target_ulong * physical,
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int *prot, target_ulong address,
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int rw, int access_type)
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{
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@ -403,7 +403,7 @@ static int get_mmu_address(CPUState * env, target_ulong * physical,
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return n;
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}
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static int get_physical_address(CPUState * env, target_ulong * physical,
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static int get_physical_address(CPUSH4State * env, target_ulong * physical,
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int *prot, target_ulong address,
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int rw, int access_type)
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{
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@ -442,7 +442,7 @@ static int get_physical_address(CPUState * env, target_ulong * physical,
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return get_mmu_address(env, physical, prot, address, rw, access_type);
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}
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int cpu_sh4_handle_mmu_fault(CPUState * env, target_ulong address, int rw,
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int cpu_sh4_handle_mmu_fault(CPUSH4State * env, target_ulong address, int rw,
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int mmu_idx)
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{
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target_ulong physical;
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@ -503,7 +503,7 @@ int cpu_sh4_handle_mmu_fault(CPUState * env, target_ulong address, int rw,
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return 0;
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}
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target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr)
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target_phys_addr_t cpu_get_phys_page_debug(CPUSH4State * env, target_ulong addr)
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{
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target_ulong physical;
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int prot;
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@ -55,10 +55,10 @@ static void cpu_restore_state_from_retaddr(void *retaddr)
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#define SHIFT 3
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#include "softmmu_template.h"
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void tlb_fill(CPUState *env1, target_ulong addr, int is_write, int mmu_idx,
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void tlb_fill(CPUSH4State *env1, target_ulong addr, int is_write, int mmu_idx,
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void *retaddr)
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{
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CPUState *saved_env;
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CPUSH4State *saved_env;
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int ret;
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saved_env = env;
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@ -103,47 +103,47 @@ static void sh4_translate_init(void)
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for (i = 0; i < 24; i++)
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cpu_gregs[i] = tcg_global_mem_new_i32(TCG_AREG0,
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offsetof(CPUState, gregs[i]),
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offsetof(CPUSH4State, gregs[i]),
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gregnames[i]);
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cpu_pc = tcg_global_mem_new_i32(TCG_AREG0,
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offsetof(CPUState, pc), "PC");
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offsetof(CPUSH4State, pc), "PC");
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cpu_sr = tcg_global_mem_new_i32(TCG_AREG0,
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offsetof(CPUState, sr), "SR");
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offsetof(CPUSH4State, sr), "SR");
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cpu_ssr = tcg_global_mem_new_i32(TCG_AREG0,
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offsetof(CPUState, ssr), "SSR");
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offsetof(CPUSH4State, ssr), "SSR");
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cpu_spc = tcg_global_mem_new_i32(TCG_AREG0,
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offsetof(CPUState, spc), "SPC");
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offsetof(CPUSH4State, spc), "SPC");
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cpu_gbr = tcg_global_mem_new_i32(TCG_AREG0,
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offsetof(CPUState, gbr), "GBR");
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offsetof(CPUSH4State, gbr), "GBR");
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cpu_vbr = tcg_global_mem_new_i32(TCG_AREG0,
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offsetof(CPUState, vbr), "VBR");
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offsetof(CPUSH4State, vbr), "VBR");
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cpu_sgr = tcg_global_mem_new_i32(TCG_AREG0,
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offsetof(CPUState, sgr), "SGR");
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offsetof(CPUSH4State, sgr), "SGR");
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cpu_dbr = tcg_global_mem_new_i32(TCG_AREG0,
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offsetof(CPUState, dbr), "DBR");
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offsetof(CPUSH4State, dbr), "DBR");
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cpu_mach = tcg_global_mem_new_i32(TCG_AREG0,
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offsetof(CPUState, mach), "MACH");
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offsetof(CPUSH4State, mach), "MACH");
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cpu_macl = tcg_global_mem_new_i32(TCG_AREG0,
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offsetof(CPUState, macl), "MACL");
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offsetof(CPUSH4State, macl), "MACL");
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cpu_pr = tcg_global_mem_new_i32(TCG_AREG0,
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offsetof(CPUState, pr), "PR");
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offsetof(CPUSH4State, pr), "PR");
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cpu_fpscr = tcg_global_mem_new_i32(TCG_AREG0,
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offsetof(CPUState, fpscr), "FPSCR");
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offsetof(CPUSH4State, fpscr), "FPSCR");
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cpu_fpul = tcg_global_mem_new_i32(TCG_AREG0,
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offsetof(CPUState, fpul), "FPUL");
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offsetof(CPUSH4State, fpul), "FPUL");
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cpu_flags = tcg_global_mem_new_i32(TCG_AREG0,
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offsetof(CPUState, flags), "_flags_");
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offsetof(CPUSH4State, flags), "_flags_");
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cpu_delayed_pc = tcg_global_mem_new_i32(TCG_AREG0,
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offsetof(CPUState, delayed_pc),
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offsetof(CPUSH4State, delayed_pc),
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"_delayed_pc_");
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cpu_ldst = tcg_global_mem_new_i32(TCG_AREG0,
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offsetof(CPUState, ldst), "_ldst_");
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offsetof(CPUSH4State, ldst), "_ldst_");
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for (i = 0; i < 32; i++)
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cpu_fregs[i] = tcg_global_mem_new_i32(TCG_AREG0,
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offsetof(CPUState, fregs[i]),
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offsetof(CPUSH4State, fregs[i]),
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fregnames[i]);
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/* register helpers */
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@ -153,7 +153,7 @@ static void sh4_translate_init(void)
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done_init = 1;
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}
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void cpu_dump_state(CPUState * env, FILE * f,
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void cpu_dump_state(CPUSH4State * env, FILE * f,
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int (*cpu_fprintf) (FILE * f, const char *fmt, ...),
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int flags)
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{
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@ -1918,7 +1918,7 @@ static void decode_opc(DisasContext * ctx)
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}
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static inline void
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gen_intermediate_code_internal(CPUState * env, TranslationBlock * tb,
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gen_intermediate_code_internal(CPUSH4State * env, TranslationBlock * tb,
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int search_pc)
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{
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DisasContext ctx;
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@ -2044,17 +2044,17 @@ gen_intermediate_code_internal(CPUState * env, TranslationBlock * tb,
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#endif
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}
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void gen_intermediate_code(CPUState * env, struct TranslationBlock *tb)
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void gen_intermediate_code(CPUSH4State * env, struct TranslationBlock *tb)
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{
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gen_intermediate_code_internal(env, tb, 0);
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}
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void gen_intermediate_code_pc(CPUState * env, struct TranslationBlock *tb)
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void gen_intermediate_code_pc(CPUSH4State * env, struct TranslationBlock *tb)
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{
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gen_intermediate_code_internal(env, tb, 1);
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}
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void restore_state_to_opc(CPUState *env, TranslationBlock *tb, int pc_pos)
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void restore_state_to_opc(CPUSH4State *env, TranslationBlock *tb, int pc_pos)
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{
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env->pc = gen_opc_pc[pc_pos];
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env->flags = gen_opc_hflags[pc_pos];
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