target/riscv: Fix the relationship between menvcfg.PBMTE/STCE and Svpbmt/Sstc extensions
menvcfg.PBMTE/STCE are read-only zero if Svpbmt/Sstc are not implemented. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20230224040852.37109-2-liweiwei@iscas.ac.cn> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
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@ -1885,10 +1885,12 @@ static RISCVException read_menvcfg(CPURISCVState *env, int csrno,
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static RISCVException write_menvcfg(CPURISCVState *env, int csrno,
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target_ulong val)
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{
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RISCVCPUConfig *cfg = &env_archcpu(env)->cfg;
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uint64_t mask = MENVCFG_FIOM | MENVCFG_CBIE | MENVCFG_CBCFE | MENVCFG_CBZE;
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if (riscv_cpu_mxl(env) == MXL_RV64) {
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mask |= MENVCFG_PBMTE | MENVCFG_STCE;
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mask |= (cfg->ext_svpbmt ? MENVCFG_PBMTE : 0) |
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(cfg->ext_sstc ? MENVCFG_STCE : 0);
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}
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env->menvcfg = (env->menvcfg & ~mask) | (val & mask);
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@ -1905,7 +1907,9 @@ static RISCVException read_menvcfgh(CPURISCVState *env, int csrno,
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static RISCVException write_menvcfgh(CPURISCVState *env, int csrno,
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target_ulong val)
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{
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uint64_t mask = MENVCFG_PBMTE | MENVCFG_STCE;
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RISCVCPUConfig *cfg = &env_archcpu(env)->cfg;
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uint64_t mask = (cfg->ext_svpbmt ? MENVCFG_PBMTE : 0) |
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(cfg->ext_sstc ? MENVCFG_STCE : 0);
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uint64_t valh = (uint64_t)val << 32;
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env->menvcfg = (env->menvcfg & ~mask) | (valh & mask);
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