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target-arm: A64: Add SP entries for EL2 and 3

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Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 1400980132-25949-10-git-send-email-edgar.iglesias@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Edgar E. Iglesias 2014-05-27 17:09:52 +01:00 committed by Peter Maydell
parent 68fdb6c5b0
commit 73fb3b764b
2 changed files with 4 additions and 4 deletions
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2
target-arm/cpu.h
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@ -163,7 +163,7 @@ typedef struct CPUARMState {
uint64_t daif; /* exception masks, in the bits they are in in PSTATE */
uint64_t elr_el[2]; /* AArch64 exception link regs */
uint64_t sp_el[2]; /* AArch64 banked stack pointers */
uint64_t sp_el[4]; /* AArch64 banked stack pointers */
/* System control coprocessor (cp15) */
struct {

6
target-arm/machine.c
View File

@ -218,8 +218,8 @@ static int cpu_post_load(void *opaque, int version_id)
const VMStateDescription vmstate_arm_cpu = {
.name = "cpu",
.version_id = 17,
.minimum_version_id = 17,
.version_id = 18,
.minimum_version_id = 18,
.pre_save = cpu_pre_save,
.post_load = cpu_post_load,
.fields = (VMStateField[]) {
@ -239,7 +239,7 @@ const VMStateDescription vmstate_arm_cpu = {
VMSTATE_UINT32_ARRAY(env.usr_regs, ARMCPU, 5),
VMSTATE_UINT32_ARRAY(env.fiq_regs, ARMCPU, 5),
VMSTATE_UINT64(env.elr_el[1], ARMCPU),
VMSTATE_UINT64_ARRAY(env.sp_el, ARMCPU, 2),
VMSTATE_UINT64_ARRAY(env.sp_el, ARMCPU, 4),
/* The length-check must come before the arrays to avoid
* incoming data possibly overflowing the array.
*/