target/hppa: Convert offset memory insns
Tested-by: Helge Deller <deller@gmx.de> Tested-by: Sven Schnelle <svens@stackframe.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson
parent
0588e061dc
commit
740038d7f5
@ -24,7 +24,9 @@
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%assemble_sr3 13:1 14:2
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%assemble_sr3x 13:1 14:2 !function=expand_sr3x
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%assemble_11a 0:s1 4:10 !function=expand_shl3
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%assemble_12 0:s1 2:1 3:10 !function=expand_shl2
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%assemble_12a 0:s1 3:11 !function=expand_shl2
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%assemble_17 0:s1 16:5 2:1 3:10 !function=expand_shl2
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%assemble_22 0:s1 16:10 2:1 3:10 !function=expand_shl2
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@ -35,9 +37,15 @@
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%sm_imm 16:10 !function=expand_sm_imm
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%rm64 1:1 16:5
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%im5_0 0:s1 1:4
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%im5_16 16:s1 17:4
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%ma_to_m 5:1 13:1 !function=ma_to_m
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%ma2_to_m 2:2 !function=ma_to_m
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%pos_to_m 0:1 !function=pos_to_m
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%neg_to_m 0:1 !function=neg_to_m
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%a_to_m 2:1 !function=neg_to_m
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####
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# Argument set definitions
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@ -187,6 +195,47 @@ lda 000011 ..... ..... .. . 0 -- 0110 ...... @ldstx size=2
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sta 000011 ..... ..... .. . 1 -- 1110 ...... @stim5 size=2
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stby 000011 b:5 r:5 sp:2 a:1 1 -- 1100 m:1 ..... disp=%im5_0
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####
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# Offset Mem
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####
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@ldstim14 ...... b:5 t:5 sp:2 .............. \
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&ldst disp=%lowsign_14 x=0 scale=0 m=0
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@ldstim14m ...... b:5 t:5 sp:2 .............. \
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&ldst disp=%lowsign_14 x=0 scale=0 m=%neg_to_m
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@ldstim12m ...... b:5 t:5 sp:2 .............. \
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&ldst disp=%assemble_12a x=0 scale=0 m=%pos_to_m
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# LDB, LDH, LDW, LDWM
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ld 010000 ..... ..... .. .............. @ldstim14 size=0
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ld 010001 ..... ..... .. .............. @ldstim14 size=1
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ld 010010 ..... ..... .. .............. @ldstim14 size=2
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ld 010011 ..... ..... .. .............. @ldstim14m size=2
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ld 010111 ..... ..... .. ...........10. @ldstim12m size=2
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# STB, STH, STW, STWM
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st 011000 ..... ..... .. .............. @ldstim14 size=0
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st 011001 ..... ..... .. .............. @ldstim14 size=1
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st 011010 ..... ..... .. .............. @ldstim14 size=2
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st 011011 ..... ..... .. .............. @ldstim14m size=2
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st 011111 ..... ..... .. ...........10. @ldstim12m size=2
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fldw 010110 b:5 ..... sp:2 .............. \
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&ldst disp=%assemble_12a t=%rm64 m=%a_to_m x=0 scale=0 size=2
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fldw 010111 b:5 ..... sp:2 ...........0.. \
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&ldst disp=%assemble_12a t=%rm64 m=0 x=0 scale=0 size=2
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fstw 011110 b:5 ..... sp:2 .............. \
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&ldst disp=%assemble_12a t=%rm64 m=%a_to_m x=0 scale=0 size=2
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fstw 011111 b:5 ..... sp:2 ...........0.. \
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&ldst disp=%assemble_12a t=%rm64 m=0 x=0 scale=0 size=2
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fldd 010100 b:5 t:5 sp:2 .......... .. 1 . \
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&ldst disp=%assemble_11a m=%ma2_to_m x=0 scale=0 size=3
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fstd 011100 b:5 t:5 sp:2 .......... .. 1 . \
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&ldst disp=%assemble_11a m=%ma2_to_m x=0 scale=0 size=3
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####
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# Floating-point Multiply Add
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####
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@ -303,12 +303,29 @@ static int ma_to_m(int val)
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return val & 2 ? (val & 1 ? -1 : 1) : 0;
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}
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/* Used for branch targets. */
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/* Convert the sign of the displacement to a pre or post-modify. */
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static int pos_to_m(int val)
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{
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return val ? 1 : -1;
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}
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static int neg_to_m(int val)
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{
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return val ? -1 : 1;
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}
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/* Used for branch targets and fp memory ops. */
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static int expand_shl2(int val)
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{
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return val << 2;
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}
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/* Used for fp memory ops. */
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static int expand_shl3(int val)
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{
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return val << 3;
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}
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/* Used for assemble_21. */
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static int expand_shl11(int val)
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{
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@ -883,24 +900,6 @@ static inline unsigned assemble_sr3(uint32_t insn)
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return s2 * 4 + s0;
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}
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static target_sreg assemble_16(uint32_t insn)
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{
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/* Take the name from PA2.0, which produces a 16-bit number
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only with wide mode; otherwise a 14-bit number. Since we don't
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implement wide mode, this is always the 14-bit number. */
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return low_sextract(insn, 0, 14);
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}
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static target_sreg assemble_16a(uint32_t insn)
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{
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/* Take the name from PA2.0, which produces a 14-bit shifted number
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only with wide mode; otherwise a 12-bit shifted number. Since we
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don't implement wide mode, this is always the 12-bit number. */
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target_ureg x = -(target_ureg)(insn & 1);
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x = (x << 11) | extract32(insn, 2, 11);
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return x << 2;
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}
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/* The parisc documentation describes only the general interpretation of
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the conditions, without describing their exact implementation. The
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interpretations do not stand up well when considering ADD,C and SUB,B.
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@ -1594,7 +1593,7 @@ static bool do_load(DisasContext *ctx, unsigned rt, unsigned rb,
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return nullify_end(ctx);
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}
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static void do_floadw(DisasContext *ctx, unsigned rt, unsigned rb,
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static bool do_floadw(DisasContext *ctx, unsigned rt, unsigned rb,
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unsigned rx, int scale, target_sreg disp,
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unsigned sp, int modify)
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{
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@ -1611,10 +1610,16 @@ static void do_floadw(DisasContext *ctx, unsigned rt, unsigned rb,
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gen_helper_loaded_fr0(cpu_env);
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}
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nullify_end(ctx);
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return nullify_end(ctx);
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}
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static void do_floadd(DisasContext *ctx, unsigned rt, unsigned rb,
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static bool trans_fldw(DisasContext *ctx, arg_ldst *a)
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{
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return do_floadw(ctx, a->t, a->b, a->x, a->scale ? 2 : 0,
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a->disp, a->sp, a->m);
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}
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static bool do_floadd(DisasContext *ctx, unsigned rt, unsigned rb,
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unsigned rx, int scale, target_sreg disp,
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unsigned sp, int modify)
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{
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@ -1631,7 +1636,13 @@ static void do_floadd(DisasContext *ctx, unsigned rt, unsigned rb,
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gen_helper_loaded_fr0(cpu_env);
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}
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nullify_end(ctx);
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return nullify_end(ctx);
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}
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static bool trans_fldd(DisasContext *ctx, arg_ldst *a)
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{
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return do_floadd(ctx, a->t, a->b, a->x, a->scale ? 3 : 0,
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a->disp, a->sp, a->m);
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}
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static bool do_store(DisasContext *ctx, unsigned rt, unsigned rb,
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@ -1643,7 +1654,7 @@ static bool do_store(DisasContext *ctx, unsigned rt, unsigned rb,
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return nullify_end(ctx);
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}
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static void do_fstorew(DisasContext *ctx, unsigned rt, unsigned rb,
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static bool do_fstorew(DisasContext *ctx, unsigned rt, unsigned rb,
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unsigned rx, int scale, target_sreg disp,
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unsigned sp, int modify)
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{
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@ -1655,10 +1666,16 @@ static void do_fstorew(DisasContext *ctx, unsigned rt, unsigned rb,
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do_store_32(ctx, tmp, rb, rx, scale, disp, sp, modify, MO_TEUL);
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tcg_temp_free_i32(tmp);
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nullify_end(ctx);
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return nullify_end(ctx);
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}
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static void do_fstored(DisasContext *ctx, unsigned rt, unsigned rb,
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static bool trans_fstw(DisasContext *ctx, arg_ldst *a)
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{
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return do_fstorew(ctx, a->t, a->b, a->x, a->scale ? 2 : 0,
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a->disp, a->sp, a->m);
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}
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static bool do_fstored(DisasContext *ctx, unsigned rt, unsigned rb,
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unsigned rx, int scale, target_sreg disp,
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unsigned sp, int modify)
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{
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@ -1670,7 +1687,13 @@ static void do_fstored(DisasContext *ctx, unsigned rt, unsigned rb,
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do_store_64(ctx, tmp, rb, rx, scale, disp, sp, modify, MO_TEQ);
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tcg_temp_free_i64(tmp);
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nullify_end(ctx);
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return nullify_end(ctx);
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}
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static bool trans_fstd(DisasContext *ctx, arg_ldst *a)
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{
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return do_fstored(ctx, a->t, a->b, a->x, a->scale ? 3 : 0,
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a->disp, a->sp, a->m);
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}
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static void do_fop_wew(DisasContext *ctx, unsigned rt, unsigned ra,
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@ -2958,107 +2981,6 @@ static bool trans_ldo(DisasContext *ctx, arg_ldo *a)
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return true;
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}
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static bool trans_load(DisasContext *ctx, uint32_t insn,
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bool is_mod, TCGMemOp mop)
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{
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unsigned rb = extract32(insn, 21, 5);
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unsigned rt = extract32(insn, 16, 5);
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unsigned sp = extract32(insn, 14, 2);
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target_sreg i = assemble_16(insn);
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do_load(ctx, rt, rb, 0, 0, i, sp, is_mod ? (i < 0 ? -1 : 1) : 0, mop);
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return true;
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}
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static bool trans_load_w(DisasContext *ctx, uint32_t insn)
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{
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unsigned rb = extract32(insn, 21, 5);
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unsigned rt = extract32(insn, 16, 5);
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unsigned sp = extract32(insn, 14, 2);
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target_sreg i = assemble_16a(insn);
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unsigned ext2 = extract32(insn, 1, 2);
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switch (ext2) {
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case 0:
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case 1:
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/* FLDW without modification. */
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do_floadw(ctx, ext2 * 32 + rt, rb, 0, 0, i, sp, 0);
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break;
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case 2:
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/* LDW with modification. Note that the sign of I selects
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post-dec vs pre-inc. */
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do_load(ctx, rt, rb, 0, 0, i, sp, (i < 0 ? 1 : -1), MO_TEUL);
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break;
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default:
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return gen_illegal(ctx);
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}
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return true;
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}
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static bool trans_fload_mod(DisasContext *ctx, uint32_t insn)
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{
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target_sreg i = assemble_16a(insn);
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unsigned t1 = extract32(insn, 1, 1);
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unsigned a = extract32(insn, 2, 1);
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unsigned sp = extract32(insn, 14, 2);
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unsigned t0 = extract32(insn, 16, 5);
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unsigned rb = extract32(insn, 21, 5);
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/* FLDW with modification. */
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do_floadw(ctx, t1 * 32 + t0, rb, 0, 0, i, sp, (a ? -1 : 1));
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return true;
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}
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static bool trans_store(DisasContext *ctx, uint32_t insn,
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bool is_mod, TCGMemOp mop)
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{
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unsigned rb = extract32(insn, 21, 5);
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unsigned rt = extract32(insn, 16, 5);
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unsigned sp = extract32(insn, 14, 2);
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target_sreg i = assemble_16(insn);
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do_store(ctx, rt, rb, i, sp, is_mod ? (i < 0 ? -1 : 1) : 0, mop);
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return true;
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}
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static bool trans_store_w(DisasContext *ctx, uint32_t insn)
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{
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unsigned rb = extract32(insn, 21, 5);
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unsigned rt = extract32(insn, 16, 5);
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unsigned sp = extract32(insn, 14, 2);
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target_sreg i = assemble_16a(insn);
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unsigned ext2 = extract32(insn, 1, 2);
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switch (ext2) {
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case 0:
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case 1:
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/* FSTW without modification. */
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do_fstorew(ctx, ext2 * 32 + rt, rb, 0, 0, i, sp, 0);
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break;
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case 2:
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/* STW with modification. */
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do_store(ctx, rt, rb, i, sp, (i < 0 ? 1 : -1), MO_TEUL);
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break;
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default:
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return gen_illegal(ctx);
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}
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return true;
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}
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static bool trans_fstore_mod(DisasContext *ctx, uint32_t insn)
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{
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target_sreg i = assemble_16a(insn);
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unsigned t1 = extract32(insn, 1, 1);
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unsigned a = extract32(insn, 2, 1);
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unsigned sp = extract32(insn, 14, 2);
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unsigned t0 = extract32(insn, 16, 5);
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unsigned rb = extract32(insn, 21, 5);
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/* FSTW with modification. */
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do_fstorew(ctx, t1 * 32 + t0, rb, 0, 0, i, sp, (a ? -1 : 1));
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return true;
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}
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static bool trans_copr_w(DisasContext *ctx, uint32_t insn)
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{
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unsigned t0 = extract32(insn, 0, 5);
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@ -4302,43 +4224,6 @@ static void translate_one(DisasContext *ctx, uint32_t insn)
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translate_table(ctx, insn, table_float_0e);
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return;
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case 0x10:
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trans_load(ctx, insn, false, MO_UB);
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return;
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case 0x11:
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trans_load(ctx, insn, false, MO_TEUW);
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return;
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case 0x12:
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trans_load(ctx, insn, false, MO_TEUL);
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return;
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case 0x13:
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trans_load(ctx, insn, true, MO_TEUL);
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return;
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case 0x16:
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trans_fload_mod(ctx, insn);
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return;
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case 0x17:
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trans_load_w(ctx, insn);
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return;
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case 0x18:
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trans_store(ctx, insn, false, MO_UB);
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return;
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case 0x19:
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trans_store(ctx, insn, false, MO_TEUW);
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return;
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case 0x1A:
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trans_store(ctx, insn, false, MO_TEUL);
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return;
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case 0x1B:
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trans_store(ctx, insn, true, MO_TEUL);
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return;
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case 0x1E:
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trans_fstore_mod(ctx, insn);
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return;
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case 0x1F:
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trans_store_w(ctx, insn);
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return;
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case 0x2E:
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translate_table(ctx, insn, table_fp_fused);
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return;
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