hw/loongarch: Change macro name 'LS7A_XXX' to 'VIRT_XXX'
Change macro name 'LS7A_XXX' to 'VIRT_XXX', as the loongarch virt machinue use the GPEX bridge instead of LS7A bridge. So the macro name should keep consistency. Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn> Message-Id: <20220729073018.27037-3-yangxiaojuan@loongson.cn> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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587858ed0d
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74725231d6
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@ -135,7 +135,7 @@ build_madt(GArray *table_data, BIOSLinker *linker, LoongArchMachineState *lams)
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build_append_int_noprefix(table_data, 21, 1); /* Type */
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build_append_int_noprefix(table_data, 19, 1); /* Length */
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build_append_int_noprefix(table_data, 1, 1); /* Version */
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build_append_int_noprefix(table_data, LS7A_PCH_MSI_ADDR_LOW, 8);/* Address */
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build_append_int_noprefix(table_data, VIRT_PCH_MSI_ADDR_LOW, 8);/* Address */
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build_append_int_noprefix(table_data, 0x40, 4); /* Start */
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build_append_int_noprefix(table_data, 0xc0, 4); /* Count */
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@ -143,7 +143,7 @@ build_madt(GArray *table_data, BIOSLinker *linker, LoongArchMachineState *lams)
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build_append_int_noprefix(table_data, 22, 1); /* Type */
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build_append_int_noprefix(table_data, 17, 1); /* Length */
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build_append_int_noprefix(table_data, 1, 1); /* Version */
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build_append_int_noprefix(table_data, LS7A_PCH_REG_BASE, 8);/* Address */
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build_append_int_noprefix(table_data, VIRT_PCH_REG_BASE, 8);/* Address */
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build_append_int_noprefix(table_data, 0x1000, 2); /* Size */
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build_append_int_noprefix(table_data, 0, 2); /* Id */
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build_append_int_noprefix(table_data, 0x40, 2); /* Base */
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@ -307,7 +307,7 @@ static void build_uart_device_aml(Aml *table)
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Aml *dev;
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Aml *crs;
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Aml *pkg0, *pkg1, *pkg2;
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uint32_t uart_irq = LS7A_UART_IRQ;
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uint32_t uart_irq = VIRT_UART_IRQ;
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Aml *scope = aml_scope("_SB");
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dev = aml_device("COMA");
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@ -367,7 +367,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, MachineState *machine)
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if (lams->acpi_ged) {
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build_ged_aml(dsdt, "\\_SB."GED_DEVICE,
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HOTPLUG_HANDLER(lams->acpi_ged),
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LS7A_SCI_IRQ - PCH_PIC_IRQ_OFFSET, AML_SYSTEM_MEMORY,
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VIRT_SCI_IRQ - PCH_PIC_IRQ_OFFSET, AML_SYSTEM_MEMORY,
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VIRT_GED_EVT_ADDR);
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}
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@ -385,9 +385,9 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, MachineState *machine)
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aml_append(crs,
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aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
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AML_CACHEABLE, AML_READ_WRITE,
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0, LS7A_PCI_MEM_BASE,
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LS7A_PCI_MEM_BASE + LS7A_PCI_MEM_SIZE - 1,
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0, LS7A_PCI_MEM_BASE));
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0, VIRT_PCI_MEM_BASE,
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VIRT_PCI_MEM_BASE + VIRT_PCI_MEM_SIZE - 1,
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0, VIRT_PCI_MEM_BASE));
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aml_append(scope, aml_name_decl("_CRS", crs));
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aml_append(dsdt, scope);
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@ -462,8 +462,8 @@ static void acpi_build(AcpiBuildTables *tables, MachineState *machine)
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acpi_add_table(table_offsets, tables_blob);
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{
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AcpiMcfgInfo mcfg = {
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.base = cpu_to_le64(LS_PCIECFG_BASE),
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.size = cpu_to_le64(LS_PCIECFG_SIZE),
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.base = cpu_to_le64(VIRT_PCI_CFG_BASE),
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.size = cpu_to_le64(VIRT_PCI_CFG_SIZE),
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};
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build_mcfg(tables_blob, tables->linker, &mcfg, lams->oem_id,
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lams->oem_table_id);
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@ -126,12 +126,12 @@ static void fdt_add_fw_cfg_node(const LoongArchMachineState *lams)
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static void fdt_add_pcie_node(const LoongArchMachineState *lams)
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{
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char *nodename;
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hwaddr base_mmio = LS7A_PCI_MEM_BASE;
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hwaddr size_mmio = LS7A_PCI_MEM_SIZE;
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hwaddr base_pio = LS7A_PCI_IO_BASE;
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hwaddr size_pio = LS7A_PCI_IO_SIZE;
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hwaddr base_pcie = LS_PCIECFG_BASE;
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hwaddr size_pcie = LS_PCIECFG_SIZE;
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hwaddr base_mmio = VIRT_PCI_MEM_BASE;
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hwaddr size_mmio = VIRT_PCI_MEM_SIZE;
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hwaddr base_pio = VIRT_PCI_IO_BASE;
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hwaddr size_pio = VIRT_PCI_IO_SIZE;
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hwaddr base_pcie = VIRT_PCI_CFG_BASE;
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hwaddr size_pcie = VIRT_PCI_CFG_SIZE;
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hwaddr base = base_pcie;
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const MachineState *ms = MACHINE(lams);
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@ -145,12 +145,12 @@ static void fdt_add_pcie_node(const LoongArchMachineState *lams)
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qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 2);
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qemu_fdt_setprop_cell(ms->fdt, nodename, "linux,pci-domain", 0);
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qemu_fdt_setprop_cells(ms->fdt, nodename, "bus-range", 0,
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PCIE_MMCFG_BUS(LS_PCIECFG_SIZE - 1));
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PCIE_MMCFG_BUS(VIRT_PCI_CFG_SIZE - 1));
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qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0);
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qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
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2, base_pcie, 2, size_pcie);
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qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "ranges",
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1, FDT_PCI_RANGE_IOPORT, 2, LS7A_PCI_IO_OFFSET,
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1, FDT_PCI_RANGE_IOPORT, 2, VIRT_PCI_IO_OFFSET,
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2, base_pio, 2, size_pio,
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1, FDT_PCI_RANGE_MMIO, 2, base_mmio,
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2, base_mmio, 2, size_mmio);
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@ -313,7 +313,7 @@ static DeviceState *create_acpi_ged(DeviceState *pch_pic, LoongArchMachineState
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sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, VIRT_GED_REG_ADDR);
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sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0,
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qdev_get_gpio_in(pch_pic, LS7A_SCI_IRQ - PCH_PIC_IRQ_OFFSET));
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qdev_get_gpio_in(pch_pic, VIRT_SCI_IRQ - PCH_PIC_IRQ_OFFSET));
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sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
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return dev;
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}
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@ -336,24 +336,24 @@ static void loongarch_devices_init(DeviceState *pch_pic, LoongArchMachineState *
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ecam_alias = g_new0(MemoryRegion, 1);
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ecam_reg = sysbus_mmio_get_region(d, 0);
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memory_region_init_alias(ecam_alias, OBJECT(gpex_dev), "pcie-ecam",
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ecam_reg, 0, LS_PCIECFG_SIZE);
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memory_region_add_subregion(get_system_memory(), LS_PCIECFG_BASE,
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ecam_reg, 0, VIRT_PCI_CFG_SIZE);
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memory_region_add_subregion(get_system_memory(), VIRT_PCI_CFG_BASE,
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ecam_alias);
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/* Map PCI mem space */
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mmio_alias = g_new0(MemoryRegion, 1);
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mmio_reg = sysbus_mmio_get_region(d, 1);
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memory_region_init_alias(mmio_alias, OBJECT(gpex_dev), "pcie-mmio",
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mmio_reg, LS7A_PCI_MEM_BASE, LS7A_PCI_MEM_SIZE);
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memory_region_add_subregion(get_system_memory(), LS7A_PCI_MEM_BASE,
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mmio_reg, VIRT_PCI_MEM_BASE, VIRT_PCI_MEM_SIZE);
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memory_region_add_subregion(get_system_memory(), VIRT_PCI_MEM_BASE,
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mmio_alias);
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/* Map PCI IO port space. */
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pio_alias = g_new0(MemoryRegion, 1);
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pio_reg = sysbus_mmio_get_region(d, 2);
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memory_region_init_alias(pio_alias, OBJECT(gpex_dev), "pcie-io", pio_reg,
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LS7A_PCI_IO_OFFSET, LS7A_PCI_IO_SIZE);
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memory_region_add_subregion(get_system_memory(), LS7A_PCI_IO_BASE,
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VIRT_PCI_IO_OFFSET, VIRT_PCI_IO_SIZE);
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memory_region_add_subregion(get_system_memory(), VIRT_PCI_IO_BASE,
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pio_alias);
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for (i = 0; i < GPEX_NUM_IRQS; i++) {
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@ -362,9 +362,9 @@ static void loongarch_devices_init(DeviceState *pch_pic, LoongArchMachineState *
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gpex_set_irq_num(GPEX_HOST(gpex_dev), i, 16 + i);
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}
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serial_mm_init(get_system_memory(), LS7A_UART_BASE, 0,
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serial_mm_init(get_system_memory(), VIRT_UART_BASE, 0,
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qdev_get_gpio_in(pch_pic,
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LS7A_UART_IRQ - PCH_PIC_IRQ_OFFSET),
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VIRT_UART_IRQ - PCH_PIC_IRQ_OFFSET),
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115200, serial_hd(0), DEVICE_LITTLE_ENDIAN);
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/* Network init */
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@ -386,9 +386,9 @@ static void loongarch_devices_init(DeviceState *pch_pic, LoongArchMachineState *
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* Create some unimplemented devices to emulate this.
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*/
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create_unimplemented_device("pci-dma-cfg", 0x1001041c, 0x4);
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sysbus_create_simple("ls7a_rtc", LS7A_RTC_REG_BASE,
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sysbus_create_simple("ls7a_rtc", VIRT_RTC_REG_BASE,
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qdev_get_gpio_in(pch_pic,
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LS7A_RTC_IRQ - PCH_PIC_IRQ_OFFSET));
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VIRT_RTC_IRQ - PCH_PIC_IRQ_OFFSET));
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pm_mem = g_new(MemoryRegion, 1);
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memory_region_init_io(pm_mem, NULL, &loongarch_virt_pm_ops,
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@ -472,13 +472,13 @@ static void loongarch_irq_init(LoongArchMachineState *lams)
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pch_pic = qdev_new(TYPE_LOONGARCH_PCH_PIC);
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d = SYS_BUS_DEVICE(pch_pic);
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sysbus_realize_and_unref(d, &error_fatal);
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memory_region_add_subregion(get_system_memory(), LS7A_IOAPIC_REG_BASE,
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memory_region_add_subregion(get_system_memory(), VIRT_IOAPIC_REG_BASE,
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sysbus_mmio_get_region(d, 0));
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memory_region_add_subregion(get_system_memory(),
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LS7A_IOAPIC_REG_BASE + PCH_PIC_ROUTE_ENTRY_OFFSET,
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VIRT_IOAPIC_REG_BASE + PCH_PIC_ROUTE_ENTRY_OFFSET,
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sysbus_mmio_get_region(d, 1));
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memory_region_add_subregion(get_system_memory(),
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LS7A_IOAPIC_REG_BASE + PCH_PIC_INT_STATUS_LO,
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VIRT_IOAPIC_REG_BASE + PCH_PIC_INT_STATUS_LO,
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sysbus_mmio_get_region(d, 2));
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/* Connect 64 pch_pic irqs to extioi */
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@ -490,7 +490,7 @@ static void loongarch_irq_init(LoongArchMachineState *lams)
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qdev_prop_set_uint32(pch_msi, "msi_irq_base", PCH_MSI_IRQ_START);
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d = SYS_BUS_DEVICE(pch_msi);
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sysbus_realize_and_unref(d, &error_fatal);
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sysbus_mmio_map(d, 0, LS7A_PCH_MSI_ADDR_LOW);
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sysbus_mmio_map(d, 0, VIRT_PCH_MSI_ADDR_LOW);
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for (i = 0; i < PCH_MSI_IRQ_NUM; i++) {
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/* Connect 192 pch_msi irqs to extioi */
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qdev_connect_gpio_out(DEVICE(d), i,
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@ -666,8 +666,8 @@ static void loongarch_init(MachineState *machine)
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memmap_add_entry(0x90000000, highram_size, 1);
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/* Add isa io region */
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memory_region_init_alias(&lams->isa_io, NULL, "isa-io",
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get_system_io(), 0, LOONGARCH_ISA_IO_SIZE);
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memory_region_add_subregion(address_space_mem, LOONGARCH_ISA_IO_BASE,
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get_system_io(), 0, VIRT_ISA_IO_SIZE);
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memory_region_add_subregion(address_space_mem, VIRT_ISA_IO_BASE,
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&lams->isa_io);
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/* load the BIOS image. */
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loongarch_firmware_init(lams);
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@ -706,9 +706,9 @@ static void loongarch_init(MachineState *machine)
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/* load fdt */
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MemoryRegion *fdt_rom = g_new(MemoryRegion, 1);
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memory_region_init_rom(fdt_rom, NULL, "fdt", LA_FDT_SIZE, &error_fatal);
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memory_region_add_subregion(get_system_memory(), LA_FDT_BASE, fdt_rom);
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rom_add_blob_fixed("fdt", machine->fdt, lams->fdt_size, LA_FDT_BASE);
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memory_region_init_rom(fdt_rom, NULL, "fdt", VIRT_FDT_SIZE, &error_fatal);
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memory_region_add_subregion(get_system_memory(), VIRT_FDT_BASE, fdt_rom);
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rom_add_blob_fixed("fdt", machine->fdt, lams->fdt_size, VIRT_FDT_BASE);
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}
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bool loongarch_is_acpi_enabled(LoongArchMachineState *lams)
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@ -15,8 +15,8 @@
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#define LOONGARCH_MAX_VCPUS 4
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#define LOONGARCH_ISA_IO_BASE 0x18000000UL
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#define LOONGARCH_ISA_IO_SIZE 0x0004000
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#define VIRT_ISA_IO_BASE 0x18000000UL
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#define VIRT_ISA_IO_SIZE 0x0004000
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#define VIRT_FWCFG_BASE 0x1e020000UL
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#define VIRT_BIOS_BASE 0x1c000000UL
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#define VIRT_BIOS_SIZE (4 * MiB)
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@ -28,8 +28,8 @@
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#define VIRT_GED_MEM_ADDR (VIRT_GED_EVT_ADDR + ACPI_GED_EVT_SEL_LEN)
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#define VIRT_GED_REG_ADDR (VIRT_GED_MEM_ADDR + MEMORY_HOTPLUG_IO_LEN)
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#define LA_FDT_BASE 0x1c400000
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#define LA_FDT_SIZE 0x100000
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#define VIRT_FDT_BASE 0x1c400000
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#define VIRT_FDT_SIZE 0x100000
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struct LoongArchMachineState {
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/*< private >*/
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@ -15,34 +15,31 @@
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#include "qemu/range.h"
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#include "qom/object.h"
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#define LS7A_PCI_MEM_BASE 0x40000000UL
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#define LS7A_PCI_MEM_SIZE 0x40000000UL
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#define LS7A_PCI_IO_OFFSET 0x4000
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#define LS_PCIECFG_BASE 0x20000000
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#define LS_PCIECFG_SIZE 0x08000000
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#define LS7A_PCI_IO_BASE 0x18004000UL
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#define LS7A_PCI_IO_SIZE 0xC000
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#define VIRT_PCI_MEM_BASE 0x40000000UL
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#define VIRT_PCI_MEM_SIZE 0x40000000UL
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#define VIRT_PCI_IO_OFFSET 0x4000
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#define VIRT_PCI_CFG_BASE 0x20000000
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#define VIRT_PCI_CFG_SIZE 0x08000000
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#define VIRT_PCI_IO_BASE 0x18004000UL
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#define VIRT_PCI_IO_SIZE 0xC000
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#define LS7A_PCI_MEM_BASE 0x40000000UL
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#define LS7A_PCI_MEM_SIZE 0x40000000UL
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#define LS7A_PCH_REG_BASE 0x10000000UL
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#define LS7A_IOAPIC_REG_BASE (LS7A_PCH_REG_BASE)
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#define LS7A_PCH_MSI_ADDR_LOW 0x2FF00000UL
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#define VIRT_PCH_REG_BASE 0x10000000UL
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#define VIRT_IOAPIC_REG_BASE (VIRT_PCH_REG_BASE)
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#define VIRT_PCH_MSI_ADDR_LOW 0x2FF00000UL
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/*
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* According to the kernel pch irq start from 64 offset
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* 0 ~ 16 irqs used for non-pci device while 16 ~ 64 irqs
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* used for pci device.
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*/
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#define PCH_PIC_IRQ_OFFSET 64
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#define LS7A_DEVICE_IRQS 16
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#define LS7A_PCI_IRQS 48
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#define LS7A_UART_IRQ (PCH_PIC_IRQ_OFFSET + 2)
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#define LS7A_UART_BASE 0x1fe001e0
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#define LS7A_RTC_IRQ (PCH_PIC_IRQ_OFFSET + 3)
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#define LS7A_MISC_REG_BASE (LS7A_PCH_REG_BASE + 0x00080000)
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#define LS7A_RTC_REG_BASE (LS7A_MISC_REG_BASE + 0x00050100)
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#define LS7A_RTC_LEN 0x100
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#define LS7A_SCI_IRQ (PCH_PIC_IRQ_OFFSET + 4)
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#define PCH_PIC_IRQ_OFFSET 64
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#define VIRT_DEVICE_IRQS 16
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#define VIRT_PCI_IRQS 48
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#define VIRT_UART_IRQ (PCH_PIC_IRQ_OFFSET + 2)
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#define VIRT_UART_BASE 0x1fe001e0
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#define VIRT_RTC_IRQ (PCH_PIC_IRQ_OFFSET + 3)
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#define VIRT_MISC_REG_BASE (VIRT_PCH_REG_BASE + 0x00080000)
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#define VIRT_RTC_REG_BASE (VIRT_MISC_REG_BASE + 0x00050100)
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#define VIRT_RTC_LEN 0x100
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#define VIRT_SCI_IRQ (PCH_PIC_IRQ_OFFSET + 4)
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#endif
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