sparc fix
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1294 c046a42c-6fe2-441c-8c8c-71466251a162
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@ -137,6 +137,8 @@ int get_physical_address (CPUState *env, target_phys_addr_t *physical, int *prot
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return 0;
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}
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*access_index = ((rw & 1) << 2) | (rw & 2) | (is_user? 0 : 1);
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/* SPARC reference MMU table walk: Context table->L1->L2->PTE */
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/* Context base + context number */
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pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 4);
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@ -146,10 +148,10 @@ int get_physical_address (CPUState *env, target_phys_addr_t *physical, int *prot
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switch (pde & PTE_ENTRYTYPE_MASK) {
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default:
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case 0: /* Invalid */
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return 1;
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return 1 << 2;
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case 2: /* L0 PTE, maybe should not happen? */
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case 3: /* Reserved */
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return 4;
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return 4 << 2;
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case 1: /* L0 PDE */
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pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4);
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pde = ldl_phys(pde_ptr);
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@ -157,9 +159,9 @@ int get_physical_address (CPUState *env, target_phys_addr_t *physical, int *prot
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switch (pde & PTE_ENTRYTYPE_MASK) {
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default:
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case 0: /* Invalid */
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return 1;
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return (1 << 8) | (1 << 2);
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case 3: /* Reserved */
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return 4;
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return (1 << 8) | (4 << 2);
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case 1: /* L1 PDE */
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pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4);
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pde = ldl_phys(pde_ptr);
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@ -167,9 +169,9 @@ int get_physical_address (CPUState *env, target_phys_addr_t *physical, int *prot
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switch (pde & PTE_ENTRYTYPE_MASK) {
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default:
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case 0: /* Invalid */
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return 1;
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return (2 << 8) | (1 << 2);
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case 3: /* Reserved */
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return 4;
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return (2 << 8) | (4 << 2);
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case 1: /* L2 PDE */
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pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4);
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pde = ldl_phys(pde_ptr);
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@ -177,10 +179,10 @@ int get_physical_address (CPUState *env, target_phys_addr_t *physical, int *prot
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switch (pde & PTE_ENTRYTYPE_MASK) {
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default:
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case 0: /* Invalid */
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return 1;
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return (3 << 8) | (1 << 2);
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case 1: /* PDE, should not happen */
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case 3: /* Reserved */
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return 4;
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return (3 << 8) | (4 << 2);
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case 2: /* L3 PTE */
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virt_addr = address & TARGET_PAGE_MASK;
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page_offset = (address & TARGET_PAGE_MASK) & (TARGET_PAGE_SIZE - 1);
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@ -206,7 +208,6 @@ int get_physical_address (CPUState *env, target_phys_addr_t *physical, int *prot
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stl_phys_notdirty(pde_ptr, pde);
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}
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/* check access */
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*access_index = ((rw & 1) << 2) | (rw & 2) | (is_user? 0 : 1);
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access_perms = (pde & PTE_ACCESS_MASK) >> PTE_ACCESS_SHIFT;
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error_code = access_table[*access_index][access_perms];
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if (error_code)
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@ -246,18 +247,28 @@ int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
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if (env->mmuregs[3]) /* Fault status register */
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env->mmuregs[3] = 1; /* overflow (not read before another fault) */
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env->mmuregs[3] |= (access_index << 5) | (error_code << 2) | 2;
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env->mmuregs[3] |= (access_index << 5) | error_code | 2;
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env->mmuregs[4] = address; /* Fault address register */
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if ((env->mmuregs[0] & MMU_NF) || env->psret == 0) {
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#if 0
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// No fault
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cpu_abort(env, "Unsupported MMU no fault case");
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vaddr = address & TARGET_PAGE_MASK;
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paddr = 0xfffff000;
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prot = PAGE_READ | PAGE_WRITE;
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ret = tlb_set_page(env, vaddr, paddr, prot, is_user, is_softmmu);
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return ret;
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#else
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cpu_abort(env, "MMU no fault case no handled");
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return 0;
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#endif
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} else {
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if (rw & 2)
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env->exception_index = TT_TFAULT;
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else
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env->exception_index = TT_DFAULT;
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return 1;
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}
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if (rw & 2)
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env->exception_index = TT_TFAULT;
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else
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env->exception_index = TT_DFAULT;
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return 1;
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}
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#endif
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