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target/arm: Enable FEAT_CSV2 for -cpu max 

This extension concerns branch speculation, which TCG does
not implement.  Thus we can trivially enable this feature.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-20-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2022-05-06 13:02:37 -05:00 committed by Peter Maydell
parent 880cd10e84
commit 74b17e1669
3 changed files with 3 additions and 0 deletions
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1
docs/system/arm/emulation.rst
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@ -12,6 +12,7 @@ the following architecture extensions:
- FEAT_BBM at level 2 (Translation table break-before-make levels)
- FEAT_BF16 (AArch64 BFloat16 instructions)
- FEAT_BTI (Branch Target Identification)
- FEAT_CSV2 (Cache speculation variant 2)
- FEAT_DIT (Data Independent Timing instructions)
- FEAT_DPB (DC CVAP instruction)
- FEAT_Debugv8p2 (Debug changes for v8.2)

1
target/arm/cpu64.c
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@ -748,6 +748,7 @@ static void aarch64_max_initfn(Object *obj)
t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);
t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* FEAT_SEL2 */
t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */
t = FIELD_DP64(t, ID_AA64PFR0, CSV2, 1); /* FEAT_CSV2 */
cpu->isar.id_aa64pfr0 = t;
t = cpu->isar.id_aa64pfr1;

1
target/arm/cpu_tcg.c
View File

@ -68,6 +68,7 @@ void aa32_max_features(ARMCPU *cpu)
cpu->isar.id_mmfr4 = t;
t = cpu->isar.id_pfr0;
t = FIELD_DP32(t, ID_PFR0, CSV2, 2); /* FEAT_CVS2 */
t = FIELD_DP32(t, ID_PFR0, DIT, 1); /* FEAT_DIT */
t = FIELD_DP32(t, ID_PFR0, RAS, 1); /* FEAT_RAS */
cpu->isar.id_pfr0 = t;