target/riscv: vector narrowing integer right shift instructions
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20200701152549.1218-16-zhiwei_liu@c-sky.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
LIU Zhiwei
Alistair Francis
parent
3277d955d2
commit
7689b028ca
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@ -432,3 +432,16 @@ DEF_HELPER_6(vsra_vx_b, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vsra_vx_h, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vsra_vx_w, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vsra_vx_d, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vnsrl_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
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DEF_HELPER_6(vnsrl_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
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DEF_HELPER_6(vnsrl_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
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DEF_HELPER_6(vnsra_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
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DEF_HELPER_6(vnsra_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
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DEF_HELPER_6(vnsra_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
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DEF_HELPER_6(vnsrl_vx_b, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vnsrl_vx_h, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vnsrl_vx_w, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vnsra_vx_b, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vnsra_vx_h, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vnsra_vx_w, void, ptr, ptr, tl, ptr, env, i32)
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@ -331,6 +331,12 @@ vsrl_vi 101000 . ..... ..... 011 ..... 1010111 @r_vm
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vsra_vv 101001 . ..... ..... 000 ..... 1010111 @r_vm
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vsra_vx 101001 . ..... ..... 100 ..... 1010111 @r_vm
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vsra_vi 101001 . ..... ..... 011 ..... 1010111 @r_vm
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vnsrl_vv 101100 . ..... ..... 000 ..... 1010111 @r_vm
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vnsrl_vx 101100 . ..... ..... 100 ..... 1010111 @r_vm
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vnsrl_vi 101100 . ..... ..... 011 ..... 1010111 @r_vm
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vnsra_vv 101101 . ..... ..... 000 ..... 1010111 @r_vm
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vnsra_vx 101101 . ..... ..... 100 ..... 1010111 @r_vm
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vnsra_vi 101101 . ..... ..... 011 ..... 1010111 @r_vm
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vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm
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vsetvl 1000000 ..... ..... 111 ..... 1010111 @r
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@ -1425,3 +1425,93 @@ GEN_OPIVX_GVEC_SHIFT_TRANS(vsra_vx, sars)
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GEN_OPIVI_GVEC_TRANS(vsll_vi, 1, vsll_vx, shli)
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GEN_OPIVI_GVEC_TRANS(vsrl_vi, 1, vsrl_vx, shri)
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GEN_OPIVI_GVEC_TRANS(vsra_vi, 1, vsra_vx, sari)
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/* Vector Narrowing Integer Right Shift Instructions */
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static bool opivv_narrow_check(DisasContext *s, arg_rmrr *a)
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{
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return (vext_check_isa_ill(s) &&
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vext_check_overlap_mask(s, a->rd, a->vm, false) &&
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vext_check_reg(s, a->rd, false) &&
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vext_check_reg(s, a->rs2, true) &&
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vext_check_reg(s, a->rs1, false) &&
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vext_check_overlap_group(a->rd, 1 << s->lmul, a->rs2,
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2 << s->lmul) &&
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(s->lmul < 0x3) && (s->sew < 0x3));
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}
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/* OPIVV with NARROW */
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#define GEN_OPIVV_NARROW_TRANS(NAME) \
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static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
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{ \
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if (opivv_narrow_check(s, a)) { \
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uint32_t data = 0; \
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static gen_helper_gvec_4_ptr * const fns[3] = { \
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gen_helper_##NAME##_b, \
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gen_helper_##NAME##_h, \
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gen_helper_##NAME##_w, \
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}; \
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TCGLabel *over = gen_new_label(); \
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tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
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\
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data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \
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data = FIELD_DP32(data, VDATA, VM, a->vm); \
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data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
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tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
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vreg_ofs(s, a->rs1), \
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vreg_ofs(s, a->rs2), cpu_env, 0, \
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s->vlen / 8, data, fns[s->sew]); \
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gen_set_label(over); \
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return true; \
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} \
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return false; \
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}
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GEN_OPIVV_NARROW_TRANS(vnsra_vv)
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GEN_OPIVV_NARROW_TRANS(vnsrl_vv)
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static bool opivx_narrow_check(DisasContext *s, arg_rmrr *a)
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{
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return (vext_check_isa_ill(s) &&
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vext_check_overlap_mask(s, a->rd, a->vm, false) &&
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vext_check_reg(s, a->rd, false) &&
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vext_check_reg(s, a->rs2, true) &&
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vext_check_overlap_group(a->rd, 1 << s->lmul, a->rs2,
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2 << s->lmul) &&
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(s->lmul < 0x3) && (s->sew < 0x3));
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}
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/* OPIVX with NARROW */
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#define GEN_OPIVX_NARROW_TRANS(NAME) \
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static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
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{ \
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if (opivx_narrow_check(s, a)) { \
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static gen_helper_opivx * const fns[3] = { \
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gen_helper_##NAME##_b, \
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gen_helper_##NAME##_h, \
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gen_helper_##NAME##_w, \
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}; \
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return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fns[s->sew], s);\
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} \
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return false; \
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}
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GEN_OPIVX_NARROW_TRANS(vnsra_vx)
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GEN_OPIVX_NARROW_TRANS(vnsrl_vx)
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/* OPIVI with NARROW */
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#define GEN_OPIVI_NARROW_TRANS(NAME, ZX, OPIVX) \
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static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
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{ \
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if (opivx_narrow_check(s, a)) { \
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static gen_helper_opivx * const fns[3] = { \
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gen_helper_##OPIVX##_b, \
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gen_helper_##OPIVX##_h, \
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gen_helper_##OPIVX##_w, \
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}; \
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return opivi_trans(a->rd, a->rs1, a->rs2, a->vm, \
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fns[s->sew], s, ZX); \
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} \
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return false; \
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}
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GEN_OPIVI_NARROW_TRANS(vnsra_vi, 1, vnsra_vx)
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GEN_OPIVI_NARROW_TRANS(vnsrl_vi, 1, vnsrl_vx)
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@ -1395,3 +1395,17 @@ GEN_VEXT_SHIFT_VX(vsra_vx_b, int8_t, int8_t, H1, H1, DO_SRL, 0x7, clearb)
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GEN_VEXT_SHIFT_VX(vsra_vx_h, int16_t, int16_t, H2, H2, DO_SRL, 0xf, clearh)
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GEN_VEXT_SHIFT_VX(vsra_vx_w, int32_t, int32_t, H4, H4, DO_SRL, 0x1f, clearl)
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GEN_VEXT_SHIFT_VX(vsra_vx_d, int64_t, int64_t, H8, H8, DO_SRL, 0x3f, clearq)
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/* Vector Narrowing Integer Right Shift Instructions */
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GEN_VEXT_SHIFT_VV(vnsrl_vv_b, uint8_t, uint16_t, H1, H2, DO_SRL, 0xf, clearb)
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GEN_VEXT_SHIFT_VV(vnsrl_vv_h, uint16_t, uint32_t, H2, H4, DO_SRL, 0x1f, clearh)
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GEN_VEXT_SHIFT_VV(vnsrl_vv_w, uint32_t, uint64_t, H4, H8, DO_SRL, 0x3f, clearl)
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GEN_VEXT_SHIFT_VV(vnsra_vv_b, uint8_t, int16_t, H1, H2, DO_SRL, 0xf, clearb)
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GEN_VEXT_SHIFT_VV(vnsra_vv_h, uint16_t, int32_t, H2, H4, DO_SRL, 0x1f, clearh)
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GEN_VEXT_SHIFT_VV(vnsra_vv_w, uint32_t, int64_t, H4, H8, DO_SRL, 0x3f, clearl)
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GEN_VEXT_SHIFT_VX(vnsrl_vx_b, uint8_t, uint16_t, H1, H2, DO_SRL, 0xf, clearb)
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GEN_VEXT_SHIFT_VX(vnsrl_vx_h, uint16_t, uint32_t, H2, H4, DO_SRL, 0x1f, clearh)
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GEN_VEXT_SHIFT_VX(vnsrl_vx_w, uint32_t, uint64_t, H4, H8, DO_SRL, 0x3f, clearl)
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GEN_VEXT_SHIFT_VX(vnsra_vx_b, int8_t, int16_t, H1, H2, DO_SRL, 0xf, clearb)
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GEN_VEXT_SHIFT_VX(vnsra_vx_h, int16_t, int32_t, H2, H4, DO_SRL, 0x1f, clearh)
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GEN_VEXT_SHIFT_VX(vnsra_vx_w, int32_t, int64_t, H4, H8, DO_SRL, 0x3f, clearl)
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