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Fourth RISC-V PR for 8.1

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* Fix LMUL check to use VLEN
 * Fix typo field in NUMA error_report
 * check priv_ver before auto-enable zca/zcd/zcf
 * Fix disas output of upper immediates
 * tidy CPU firmware section
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Merge tag 'pull-riscv-to-apply-20230719-1' of https://github.com/alistair23/qemu into staging

Fourth RISC-V PR for 8.1

* Fix LMUL check to use VLEN
* Fix typo field in NUMA error_report
* check priv_ver before auto-enable zca/zcd/zcf
* Fix disas output of upper immediates
* tidy CPU firmware section

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* tag 'pull-riscv-to-apply-20230719-1' of https://github.com/alistair23/qemu:
  target/riscv: Fix LMUL check to use VLEN
  hw/riscv: Fix typo field in error_report
  target/riscv/cpu.c: check priv_ver before auto-enable zca/zcd/zcf
  riscv/disas: Fix disas output of upper immediates
  docs/system/target-riscv.rst: tidy CPU firmware section

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2023-07-19 13:42:17 +01:00
commit 76e6a2ca9e
6 changed files with 40 additions and 16 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

19
disas/riscv.c
View File

@ -1135,8 +1135,8 @@ static const rv_comp_data rvcp_fsgnjx_q[] = {
const rv_opcode_data rvi_opcode_data[] = {
{ "illegal", rv_codec_illegal, rv_fmt_none, NULL, 0, 0, 0 },
{ "lui", rv_codec_u, rv_fmt_rd_imm, NULL, 0, 0, 0 },
{ "auipc", rv_codec_u, rv_fmt_rd_offset, NULL, 0, 0, 0 },
{ "lui", rv_codec_u, rv_fmt_rd_uimm, NULL, 0, 0, 0 },
{ "auipc", rv_codec_u, rv_fmt_rd_uoffset, NULL, 0, 0, 0 },
{ "jal", rv_codec_uj, rv_fmt_rd_offset, rvcp_jal, 0, 0, 0 },
{ "jalr", rv_codec_i, rv_fmt_rd_rs1_offset, rvcp_jalr, 0, 0, 0 },
{ "beq", rv_codec_sb, rv_fmt_rs1_rs2_offset, rvcp_beq, 0, 0, 0 },
@ -1382,7 +1382,7 @@ const rv_opcode_data rvi_opcode_data[] = {
rv_op_addi },
{ "c.addi16sp", rv_codec_ci_16sp, rv_fmt_rd_rs1_imm, NULL, rv_op_addi,
rv_op_addi, rv_op_addi, rvcd_imm_nz },
{ "c.lui", rv_codec_ci_lui, rv_fmt_rd_imm, NULL, rv_op_lui, rv_op_lui,
{ "c.lui", rv_codec_ci_lui, rv_fmt_rd_uimm, NULL, rv_op_lui, rv_op_lui,
rv_op_lui, rvcd_imm_nz },
{ "c.srli", rv_codec_cb_sh6, rv_fmt_rd_rs1_imm, NULL, rv_op_srli,
rv_op_srli, rv_op_srli, rvcd_imm_nz },
@ -4694,6 +4694,19 @@ static void format_inst(char *buf, size_t buflen, size_t tab, rv_decode *dec)
dec->pc + dec->imm);
append(buf, tmp, buflen);
break;
case 'U':
fmt++;
snprintf(tmp, sizeof(tmp), "%d", dec->imm >> 12);
append(buf, tmp, buflen);
if (*fmt == 'o') {
while (strlen(buf) < tab * 2) {
append(buf, " ", buflen);
}
snprintf(tmp, sizeof(tmp), "# 0x%" PRIx64,
dec->pc + dec->imm);
append(buf, tmp, buflen);
}
break;
case 'c': {
const char *name = csr_name(dec->imm & 0xfff);
if (name) {

2
disas/riscv.h
View File

@ -227,7 +227,9 @@ enum {
#define rv_fmt_pred_succ "O\tp,s"
#define rv_fmt_rs1_rs2 "O\t1,2"
#define rv_fmt_rd_imm "O\t0,i"
#define rv_fmt_rd_uimm "O\t0,Ui"
#define rv_fmt_rd_offset "O\t0,o"
#define rv_fmt_rd_uoffset "O\t0,Uo"
#define rv_fmt_rd_rs1_rs2 "O\t0,1,2"
#define rv_fmt_frd_rs1 "O\t3,1"
#define rv_fmt_frd_rs1_rs2 "O\t3,1,2"

24
docs/system/target-riscv.rst
View File

@ -76,11 +76,19 @@ RISC-V CPU firmware
When using the ``sifive_u`` or ``virt`` machine there are three different
firmware boot options:
1. ``-bios default`` - This is the default behaviour if no -bios option
is included. This option will load the default OpenSBI firmware automatically.
The firmware is included with the QEMU release and no user interaction is
required. All a user needs to do is specify the kernel they want to boot
with the -kernel option
2. ``-bios none`` - QEMU will not automatically load any firmware. It is up
to the user to load all the images they need.
3. ``-bios <file>`` - Tells QEMU to load the specified file as the firmware.
* ``-bios default``
This is the default behaviour if no ``-bios`` option is included. This option
will load the default OpenSBI firmware automatically. The firmware is included
with the QEMU release and no user interaction is required. All a user needs to
do is specify the kernel they want to boot with the ``-kernel`` option
* ``-bios none``
QEMU will not automatically load any firmware. It is up to the user to load all
the images they need.
* ``-bios <file>``
Tells QEMU to load the specified file as the firmware.

4
hw/riscv/numa.c
View File

@ -209,8 +209,8 @@ int64_t riscv_numa_get_default_cpu_node_id(const MachineState *ms, int idx)
if (ms->numa_state->num_nodes > ms->smp.cpus) {
error_report("Number of NUMA nodes (%d)"
" cannot exceed the number of available CPUs (%d).",
ms->numa_state->num_nodes, ms->smp.max_cpus);
" cannot exceed the number of available CPUs (%u).",
ms->numa_state->num_nodes, ms->smp.cpus);
exit(EXIT_FAILURE);
}
if (ms->numa_state->num_nodes) {

3
target/riscv/cpu.c
View File

@ -1225,7 +1225,8 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
}
}
if (riscv_has_ext(env, RVC)) {
/* zca, zcd and zcf has a PRIV 1.12.0 restriction */
if (riscv_has_ext(env, RVC) && env->priv_ver >= PRIV_VERSION_1_12_0) {
cpu->cfg.ext_zca = true;
if (riscv_has_ext(env, RVF) && env->misa_mxl_max == MXL_RV32) {
cpu->cfg.ext_zcf = true;

4
target/riscv/vector_helper.c
View File

@ -43,9 +43,9 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
xlen - 1 - R_VTYPE_RESERVED_SHIFT);
if (lmul & 4) {
/* Fractional LMUL. */
/* Fractional LMUL - check LMUL * VLEN >= SEW */
if (lmul == 4 ||
cpu->cfg.elen >> (8 - lmul) < sew) {
cpu->cfg.vlen >> (8 - lmul) < sew) {
vill = true;
}
}