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target/microblaze: Split out PC from env->sregs 

Begin eliminating the sregs array in favor of individual members.
Does not correct the width of pc, yet.

Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2020-08-19 21:33:32 -07:00
parent 8a42ddf013
commit 76e8187d00
9 changed files with 42 additions and 37 deletions
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12
linux-user/microblaze/cpu_loop.c
View File

@ -51,7 +51,7 @@ void cpu_loop(CPUMBState *env)
case EXCP_BREAK:
/* Return address is 4 bytes after the call. */
env->regs[14] += 4;
env->sregs[SR_PC] = env->regs[14];
env->pc = env->regs[14];
ret = do_syscall(env,
env->regs[12],
env->regs[5],
@ -63,7 +63,7 @@ void cpu_loop(CPUMBState *env)
0, 0);
if (ret == -TARGET_ERESTARTSYS) {
/* Wind back to before the syscall. */
env->sregs[SR_PC] -= 4;
env->pc -= 4;
} else if (ret != -TARGET_QEMU_ESIGRETURN) {
env->regs[3] = ret;
}
@ -73,13 +73,13 @@ void cpu_loop(CPUMBState *env)
* not a userspace-usable register, as the kernel may clobber it
* at any point.)
*/
env->regs[14] = env->sregs[SR_PC];
env->regs[14] = env->pc;
break;
case EXCP_HW_EXCP:
env->regs[17] = env->sregs[SR_PC] + 4;
env->regs[17] = env->pc + 4;
if (env->iflags & D_FLAG) {
env->sregs[SR_ESR] |= 1 << 12;
env->sregs[SR_PC] -= 4;
env->pc -= 4;
/* FIXME: if branch was immed, replay the imm as well. */
}
@ -165,5 +165,5 @@ void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs)
env->regs[29] = regs->r29;
env->regs[30] = regs->r30;
env->regs[31] = regs->r31;
env->sregs[SR_PC] = regs->pc;
env->pc = regs->pc;
}

8
linux-user/microblaze/signal.c
View File

@ -87,7 +87,7 @@ static void setup_sigcontext(struct target_sigcontext *sc, CPUMBState *env)
__put_user(env->regs[29], &sc->regs.r29);
__put_user(env->regs[30], &sc->regs.r30);
__put_user(env->regs[31], &sc->regs.r31);
__put_user(env->sregs[SR_PC], &sc->regs.pc);
__put_user(env->pc, &sc->regs.pc);
}
static void restore_sigcontext(struct target_sigcontext *sc, CPUMBState *env)
@ -124,7 +124,7 @@ static void restore_sigcontext(struct target_sigcontext *sc, CPUMBState *env)
__get_user(env->regs[29], &sc->regs.r29);
__get_user(env->regs[30], &sc->regs.r30);
__get_user(env->regs[31], &sc->regs.r31);
__get_user(env->sregs[SR_PC], &sc->regs.pc);
__get_user(env->pc, &sc->regs.pc);
}
static abi_ulong get_sigframe(struct target_sigaction *ka,
@ -188,7 +188,7 @@ void setup_frame(int sig, struct target_sigaction *ka,
env->regs[7] = frame_addr += offsetof(typeof(*frame), uc);
/* Offset of 4 to handle microblaze rtid r14, 0 */
env->sregs[SR_PC] = (unsigned long)ka->_sa_handler;
env->pc = (unsigned long)ka->_sa_handler;
unlock_user_struct(frame, frame_addr, 1);
return;
@ -228,7 +228,7 @@ long do_sigreturn(CPUMBState *env)
restore_sigcontext(&frame->uc.tuc_mcontext, env);
/* We got here through a sigreturn syscall, our path back is via an
rtb insn so setup r14 for that. */
env->regs[14] = env->sregs[SR_PC];
env->regs[14] = env->pc;
unlock_user_struct(frame, frame_addr, 0);
return -TARGET_QEMU_ESIGRETURN;

4
target/microblaze/cpu.c
View File

@ -79,7 +79,7 @@ static void mb_cpu_set_pc(CPUState *cs, vaddr value)
{
MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
cpu->env.sregs[SR_PC] = value;
cpu->env.pc = value;
}
static bool mb_cpu_has_work(CPUState *cs)
@ -117,7 +117,7 @@ static void mb_cpu_reset(DeviceState *dev)
/* Disable stack protector. */
env->shr = ~0;
env->sregs[SR_PC] = cpu->cfg.base_vectors;
env->pc = cpu->cfg.base_vectors;
#if defined(CONFIG_USER_ONLY)
/* start in user mode with interrupts enabled. */

3
target/microblaze/cpu.h
View File

@ -236,6 +236,7 @@ struct CPUMBState {
uint32_t imm;
uint32_t regs[32];
uint64_t pc;
uint64_t sregs[14];
float_status fp_status;
/* Stack protectors. Yes, it's a hw feature. */
@ -351,7 +352,7 @@ typedef MicroBlazeCPU ArchCPU;
static inline void cpu_get_tb_cpu_state(CPUMBState *env, target_ulong *pc,
target_ulong *cs_base, uint32_t *flags)
{
*pc = env->sregs[SR_PC];
*pc = env->pc;
*cs_base = 0;
*flags = (env->iflags & IFLAGS_TB_MASK) |
(env->sregs[SR_MSR] & (MSR_UM | MSR_VM | MSR_EE));

4
target/microblaze/gdbstub.c
View File

@ -59,7 +59,7 @@ int mb_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
val = env->regs[n];
break;
case GDB_PC:
val = env->sregs[SR_PC];
val = env->pc;
break;
case GDB_MSR:
val = env->sregs[SR_MSR];
@ -115,7 +115,7 @@ int mb_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
env->regs[n] = tmp;
break;
case GDB_PC:
env->sregs[SR_PC] = tmp;
env->pc = tmp;
break;
case GDB_MSR:
env->sregs[SR_MSR] = tmp;

34
target/microblaze/helper.c
View File

@ -35,7 +35,7 @@ void mb_cpu_do_interrupt(CPUState *cs)
cs->exception_index = -1;
env->res_addr = RES_ADDR_NONE;
env->regs[14] = env->sregs[SR_PC];
env->regs[14] = env->pc;
}
bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
@ -126,7 +126,7 @@ void mb_cpu_do_interrupt(CPUState *cs)
return;
}
env->regs[17] = env->sregs[SR_PC] + 4;
env->regs[17] = env->pc + 4;
env->sregs[SR_ESR] &= ~(1 << 12);
/* Exception breaks branch + dslot sequence? */
@ -145,15 +145,15 @@ void mb_cpu_do_interrupt(CPUState *cs)
qemu_log_mask(CPU_LOG_INT,
"hw exception at pc=%" PRIx64 " ear=%" PRIx64 " "
"esr=%" PRIx64 " iflags=%x\n",
env->sregs[SR_PC], env->sregs[SR_EAR],
env->pc, env->sregs[SR_EAR],
env->sregs[SR_ESR], env->iflags);
log_cpu_state_mask(CPU_LOG_INT, cs, 0);
env->iflags &= ~(IMM_FLAG | D_FLAG);
env->sregs[SR_PC] = cpu->cfg.base_vectors + 0x20;
env->pc = cpu->cfg.base_vectors + 0x20;
break;
case EXCP_MMU:
env->regs[17] = env->sregs[SR_PC];
env->regs[17] = env->pc;
env->sregs[SR_ESR] &= ~(1 << 12);
/* Exception breaks branch + dslot sequence? */
@ -169,7 +169,7 @@ void mb_cpu_do_interrupt(CPUState *cs)
qemu_log_mask(CPU_LOG_INT,
"bimm exception at pc=%" PRIx64 " "
"iflags=%x\n",
env->sregs[SR_PC], env->iflags);
env->pc, env->iflags);
env->regs[17] -= 4;
log_cpu_state_mask(CPU_LOG_INT, cs, 0);
}
@ -188,10 +188,10 @@ void mb_cpu_do_interrupt(CPUState *cs)
qemu_log_mask(CPU_LOG_INT,
"exception at pc=%" PRIx64 " ear=%" PRIx64 " "
"iflags=%x\n",
env->sregs[SR_PC], env->sregs[SR_EAR], env->iflags);
env->pc, env->sregs[SR_EAR], env->iflags);
log_cpu_state_mask(CPU_LOG_INT, cs, 0);
env->iflags &= ~(IMM_FLAG | D_FLAG);
env->sregs[SR_PC] = cpu->cfg.base_vectors + 0x20;
env->pc = cpu->cfg.base_vectors + 0x20;
break;
case EXCP_IRQ:
@ -209,14 +209,14 @@ void mb_cpu_do_interrupt(CPUState *cs)
{
const char *sym;
sym = lookup_symbol(env->sregs[SR_PC]);
sym = lookup_symbol(env->pc);
if (sym
&& (!strcmp("netif_rx", sym)
|| !strcmp("process_backlog", sym))) {
qemu_log(
"interrupt at pc=%x msr=%x %x iflags=%x sym=%s\n",
env->sregs[SR_PC], env->sregs[SR_MSR], t, env->iflags,
env->pc, env->sregs[SR_MSR], t, env->iflags,
sym);
log_cpu_state(cs, 0);
@ -226,14 +226,14 @@ void mb_cpu_do_interrupt(CPUState *cs)
qemu_log_mask(CPU_LOG_INT,
"interrupt at pc=%" PRIx64 " msr=%" PRIx64 " %x "
"iflags=%x\n",
env->sregs[SR_PC], env->sregs[SR_MSR], t, env->iflags);
env->pc, env->sregs[SR_MSR], t, env->iflags);
env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM \
| MSR_UM | MSR_IE);
env->sregs[SR_MSR] |= t;
env->regs[14] = env->sregs[SR_PC];
env->sregs[SR_PC] = cpu->cfg.base_vectors + 0x10;
env->regs[14] = env->pc;
env->pc = cpu->cfg.base_vectors + 0x10;
//log_cpu_state_mask(CPU_LOG_INT, cs, 0);
break;
@ -245,17 +245,17 @@ void mb_cpu_do_interrupt(CPUState *cs)
qemu_log_mask(CPU_LOG_INT,
"break at pc=%" PRIx64 " msr=%" PRIx64 " %x "
"iflags=%x\n",
env->sregs[SR_PC], env->sregs[SR_MSR], t, env->iflags);
env->pc, env->sregs[SR_MSR], t, env->iflags);
log_cpu_state_mask(CPU_LOG_INT, cs, 0);
env->sregs[SR_MSR] &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM);
env->sregs[SR_MSR] |= t;
env->sregs[SR_MSR] |= MSR_BIP;
if (cs->exception_index == EXCP_HW_BREAK) {
env->regs[16] = env->sregs[SR_PC];
env->regs[16] = env->pc;
env->sregs[SR_MSR] |= MSR_BIP;
env->sregs[SR_PC] = cpu->cfg.base_vectors + 0x18;
env->pc = cpu->cfg.base_vectors + 0x18;
} else
env->sregs[SR_PC] = env->btarget;
env->pc = env->btarget;
break;
default:
cpu_abort(cs, "unhandled exception type=%d\n",

2
target/microblaze/mmu.c
View File

@ -251,7 +251,7 @@ void mmu_write(CPUMBState *env, bool ext, uint32_t rn, uint32_t v)
if (i < 3 && !(v & TLB_VALID) && qemu_loglevel_mask(~0))
qemu_log_mask(LOG_GUEST_ERROR,
"invalidating index %x at pc=%" PRIx64 "\n",
i, env->sregs[SR_PC]);
i, env->pc);
env->mmu.tids[i] = env->mmu.regs[MMU_R_PID] & 0xff;
mmu_flush_idx(env, i);
}

2
target/microblaze/op_helper.c
View File

@ -75,7 +75,7 @@ void helper_debug(CPUMBState *env)
{
int i;
qemu_log("PC=%" PRIx64 "\n", env->sregs[SR_PC]);
qemu_log("PC=%" PRIx64 "\n", env->pc);
qemu_log("rmsr=%" PRIx64 " resr=%" PRIx64 " rear=%" PRIx64 " "
"debug[%x] imm=%x iflags=%x\n",
env->sregs[SR_MSR], env->sregs[SR_ESR], env->sregs[SR_EAR],

10
target/microblaze/translate.c
View File

@ -1805,7 +1805,7 @@ void mb_cpu_dump_state(CPUState *cs, FILE *f, int flags)
}
qemu_fprintf(f, "IN: PC=%" PRIx64 " %s\n",
env->sregs[SR_PC], lookup_symbol(env->sregs[SR_PC]));
env->pc, lookup_symbol(env->pc));
qemu_fprintf(f, "rmsr=%" PRIx64 " resr=%" PRIx64 " rear=%" PRIx64 " "
"debug=%x imm=%x iflags=%x fsr=%" PRIx64 " "
"rbtr=%" PRIx64 "\n",
@ -1868,7 +1868,11 @@ void mb_tcg_init(void)
offsetof(CPUMBState, regs[i]),
regnames[i]);
}
for (i = 0; i < ARRAY_SIZE(cpu_SR); i++) {
cpu_SR[SR_PC] =
tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, pc), "rpc");
for (i = 1; i < ARRAY_SIZE(cpu_SR); i++) {
cpu_SR[i] = tcg_global_mem_new_i64(cpu_env,
offsetof(CPUMBState, sregs[i]),
special_regnames[i]);
@ -1878,5 +1882,5 @@ void mb_tcg_init(void)
void restore_state_to_opc(CPUMBState *env, TranslationBlock *tb,
target_ulong *data)
{
env->sregs[SR_PC] = data[0];
env->pc = data[0];
}