hw/intc/arm_gicv3: Implement ICV_ registers which are just accessors
If the HCR_EL2.IMO or FMO bits are set, accesses to ICC_ system registers are redirected to be accesses to ICV_ registers (the guest-visible interface to the virtual interrupt controller). Implement this behaviour for the ICV_ registers which are simple accessors to the underlying register state. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1483977924-14522-10-git-send-email-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell
parent
83f036fe3d
commit
77620ba65e
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@ -13,6 +13,7 @@
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*/
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#include "qemu/osdep.h"
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#include "qemu/bitops.h"
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#include "trace.h"
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#include "gicv3_internal.h"
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#include "cpu.h"
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@ -48,6 +49,26 @@ static int ich_lr_state(uint64_t lr)
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return extract64(lr, ICH_LR_EL2_STATE_SHIFT, ICH_LR_EL2_STATE_LENGTH);
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}
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static bool icv_access(CPUARMState *env, int hcr_flags)
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{
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/* Return true if this ICC_ register access should really be
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* directed to an ICV_ access. hcr_flags is a mask of
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* HCR_EL2 bits to check: we treat this as an ICV_ access
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* if we are in NS EL1 and at least one of the specified
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* HCR_EL2 bits is set.
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*
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* ICV registers fall into four categories:
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* * access if NS EL1 and HCR_EL2.FMO == 1:
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* all ICV regs with '0' in their name
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* * access if NS EL1 and HCR_EL2.IMO == 1:
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* all ICV regs with '1' in their name
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* * access if NS EL1 and either IMO or FMO == 1:
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* CTLR, DIR, PMR, RPR
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*/
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return (env->cp15.hcr_el2 & hcr_flags) && arm_current_el(env) == 1
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&& !arm_is_secure_below_el3(env);
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}
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static int read_vbpr(GICv3CPUState *cs, int grp)
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{
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/* Read VBPR value out of the VMCR field (caller must handle
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@ -84,6 +105,16 @@ static void write_vbpr(GICv3CPUState *cs, int grp, int value)
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}
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}
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static uint32_t icv_fullprio_mask(GICv3CPUState *cs)
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{
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/* Return a mask word which clears the unimplemented priority bits
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* from a priority value for a virtual interrupt. (Not to be confused
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* with the group priority, whose mask depends on the value of VBPR
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* for the interrupt group.)
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*/
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return ~0U << (8 - cs->vpribits);
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}
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static uint32_t eoi_maintenance_interrupt_state(GICv3CPUState *cs,
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uint32_t *misr)
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{
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@ -168,6 +199,170 @@ static void gicv3_cpuif_virt_update(GICv3CPUState *cs)
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{
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}
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static uint64_t icv_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
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{
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GICv3CPUState *cs = icc_cs_from_env(env);
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int regno = ri->opc2 & 3;
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int grp = ri->crm & 1 ? GICV3_G0 : GICV3_G1NS;
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uint64_t value = cs->ich_apr[grp][regno];
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trace_gicv3_icv_ap_read(ri->crm & 1, regno, gicv3_redist_affid(cs), value);
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return value;
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}
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static void icv_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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{
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GICv3CPUState *cs = icc_cs_from_env(env);
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int regno = ri->opc2 & 3;
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int grp = ri->crm & 1 ? GICV3_G0 : GICV3_G1NS;
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trace_gicv3_icv_ap_write(ri->crm & 1, regno, gicv3_redist_affid(cs), value);
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cs->ich_apr[grp][regno] = value & 0xFFFFFFFFU;
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gicv3_cpuif_virt_update(cs);
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return;
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}
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static uint64_t icv_bpr_read(CPUARMState *env, const ARMCPRegInfo *ri)
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{
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GICv3CPUState *cs = icc_cs_from_env(env);
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int grp = (ri->crm == 8) ? GICV3_G0 : GICV3_G1NS;
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uint64_t bpr;
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bool satinc = false;
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if (grp == GICV3_G1NS && (cs->ich_vmcr_el2 & ICH_VMCR_EL2_VCBPR)) {
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/* reads return bpr0 + 1 saturated to 7, writes ignored */
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grp = GICV3_G0;
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satinc = true;
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}
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bpr = read_vbpr(cs, grp);
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if (satinc) {
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bpr++;
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bpr = MIN(bpr, 7);
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}
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trace_gicv3_icv_bpr_read(ri->crm == 8 ? 0 : 1, gicv3_redist_affid(cs), bpr);
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return bpr;
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}
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static void icv_bpr_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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{
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GICv3CPUState *cs = icc_cs_from_env(env);
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int grp = (ri->crm == 8) ? GICV3_G0 : GICV3_G1NS;
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trace_gicv3_icv_bpr_write(ri->crm == 8 ? 0 : 1,
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gicv3_redist_affid(cs), value);
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if (grp == GICV3_G1NS && (cs->ich_vmcr_el2 & ICH_VMCR_EL2_VCBPR)) {
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/* reads return bpr0 + 1 saturated to 7, writes ignored */
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return;
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}
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write_vbpr(cs, grp, value);
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gicv3_cpuif_virt_update(cs);
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}
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static uint64_t icv_pmr_read(CPUARMState *env, const ARMCPRegInfo *ri)
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{
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GICv3CPUState *cs = icc_cs_from_env(env);
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uint64_t value;
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value = extract64(cs->ich_vmcr_el2, ICH_VMCR_EL2_VPMR_SHIFT,
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ICH_VMCR_EL2_VPMR_LENGTH);
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trace_gicv3_icv_pmr_read(gicv3_redist_affid(cs), value);
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return value;
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}
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static void icv_pmr_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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{
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GICv3CPUState *cs = icc_cs_from_env(env);
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trace_gicv3_icv_pmr_write(gicv3_redist_affid(cs), value);
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value &= icv_fullprio_mask(cs);
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cs->ich_vmcr_el2 = deposit64(cs->ich_vmcr_el2, ICH_VMCR_EL2_VPMR_SHIFT,
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ICH_VMCR_EL2_VPMR_LENGTH, value);
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gicv3_cpuif_virt_update(cs);
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}
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static uint64_t icv_igrpen_read(CPUARMState *env, const ARMCPRegInfo *ri)
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{
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GICv3CPUState *cs = icc_cs_from_env(env);
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int enbit;
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uint64_t value;
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enbit = ri->opc2 & 1 ? ICH_VMCR_EL2_VENG1_SHIFT : ICH_VMCR_EL2_VENG0_SHIFT;
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value = extract64(cs->ich_vmcr_el2, enbit, 1);
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trace_gicv3_icv_igrpen_read(ri->opc2 & 1 ? 1 : 0,
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gicv3_redist_affid(cs), value);
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return value;
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}
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static void icv_igrpen_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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{
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GICv3CPUState *cs = icc_cs_from_env(env);
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int enbit;
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trace_gicv3_icv_igrpen_write(ri->opc2 & 1 ? 1 : 0,
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gicv3_redist_affid(cs), value);
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enbit = ri->opc2 & 1 ? ICH_VMCR_EL2_VENG1_SHIFT : ICH_VMCR_EL2_VENG0_SHIFT;
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cs->ich_vmcr_el2 = deposit64(cs->ich_vmcr_el2, enbit, 1, value);
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gicv3_cpuif_virt_update(cs);
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}
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static uint64_t icv_ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
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{
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GICv3CPUState *cs = icc_cs_from_env(env);
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uint64_t value;
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/* Note that the fixed fields here (A3V, SEIS, IDbits, PRIbits)
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* should match the ones reported in ich_vtr_read().
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*/
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value = ICC_CTLR_EL1_A3V | (1 << ICC_CTLR_EL1_IDBITS_SHIFT) |
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(7 << ICC_CTLR_EL1_PRIBITS_SHIFT);
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if (cs->ich_vmcr_el2 & ICH_VMCR_EL2_VEOIM) {
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value |= ICC_CTLR_EL1_EOIMODE;
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}
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if (cs->ich_vmcr_el2 & ICH_VMCR_EL2_VCBPR) {
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value |= ICC_CTLR_EL1_CBPR;
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}
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trace_gicv3_icv_ctlr_read(gicv3_redist_affid(cs), value);
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return value;
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}
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static void icv_ctlr_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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{
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GICv3CPUState *cs = icc_cs_from_env(env);
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trace_gicv3_icv_ctlr_write(gicv3_redist_affid(cs), value);
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cs->ich_vmcr_el2 = deposit64(cs->ich_vmcr_el2, ICH_VMCR_EL2_VCBPR_SHIFT,
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1, value & ICC_CTLR_EL1_CBPR ? 1 : 0);
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cs->ich_vmcr_el2 = deposit64(cs->ich_vmcr_el2, ICH_VMCR_EL2_VEOIM_SHIFT,
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1, value & ICC_CTLR_EL1_EOIMODE ? 1 : 0);
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gicv3_cpuif_virt_update(cs);
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}
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static int icc_highest_active_prio(GICv3CPUState *cs)
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{
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/* Calculate the current running priority based on the set bits
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@ -309,6 +504,10 @@ static uint64_t icc_pmr_read(CPUARMState *env, const ARMCPRegInfo *ri)
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GICv3CPUState *cs = icc_cs_from_env(env);
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uint32_t value = cs->icc_pmr_el1;
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if (icv_access(env, HCR_FMO | HCR_IMO)) {
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return icv_pmr_read(env, ri);
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}
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if (arm_feature(env, ARM_FEATURE_EL3) && !arm_is_secure(env) &&
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(env->cp15.scr_el3 & SCR_FIQ)) {
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/* NS access and Group 0 is inaccessible to NS: return the
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@ -332,6 +531,10 @@ static void icc_pmr_write(CPUARMState *env, const ARMCPRegInfo *ri,
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{
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GICv3CPUState *cs = icc_cs_from_env(env);
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if (icv_access(env, HCR_FMO | HCR_IMO)) {
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return icv_pmr_write(env, ri, value);
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}
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trace_gicv3_icc_pmr_write(gicv3_redist_affid(cs), value);
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value &= 0xff;
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@ -650,6 +853,10 @@ static uint64_t icc_bpr_read(CPUARMState *env, const ARMCPRegInfo *ri)
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bool satinc = false;
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uint64_t bpr;
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if (icv_access(env, grp == GICV3_G0 ? HCR_FMO : HCR_IMO)) {
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return icv_bpr_read(env, ri);
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}
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if (grp == GICV3_G1 && gicv3_use_ns_bank(env)) {
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grp = GICV3_G1NS;
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}
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@ -686,6 +893,11 @@ static void icc_bpr_write(CPUARMState *env, const ARMCPRegInfo *ri,
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GICv3CPUState *cs = icc_cs_from_env(env);
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int grp = (ri->crm == 8) ? GICV3_G0 : GICV3_G1;
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if (icv_access(env, grp == GICV3_G0 ? HCR_FMO : HCR_IMO)) {
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icv_bpr_write(env, ri, value);
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return;
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}
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trace_gicv3_icc_bpr_write(ri->crm == 8 ? 0 : 1,
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gicv3_redist_affid(cs), value);
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@ -719,6 +931,10 @@ static uint64_t icc_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
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int regno = ri->opc2 & 3;
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int grp = ri->crm & 1 ? GICV3_G0 : GICV3_G1;
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if (icv_access(env, grp == GICV3_G0 ? HCR_FMO : HCR_IMO)) {
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return icv_ap_read(env, ri);
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}
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if (grp == GICV3_G1 && gicv3_use_ns_bank(env)) {
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grp = GICV3_G1NS;
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}
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@ -737,6 +953,11 @@ static void icc_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
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int regno = ri->opc2 & 3;
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int grp = ri->crm & 1 ? GICV3_G0 : GICV3_G1;
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if (icv_access(env, grp == GICV3_G0 ? HCR_FMO : HCR_IMO)) {
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icv_ap_write(env, ri, value);
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return;
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}
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trace_gicv3_icc_ap_write(ri->crm & 1, regno, gicv3_redist_affid(cs), value);
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if (grp == GICV3_G1 && gicv3_use_ns_bank(env)) {
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@ -949,6 +1170,10 @@ static uint64_t icc_igrpen_read(CPUARMState *env, const ARMCPRegInfo *ri)
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int grp = ri->opc2 & 1 ? GICV3_G1 : GICV3_G0;
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uint64_t value;
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if (icv_access(env, grp == GICV3_G0 ? HCR_FMO : HCR_IMO)) {
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return icv_igrpen_read(env, ri);
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}
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if (grp == GICV3_G1 && gicv3_use_ns_bank(env)) {
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grp = GICV3_G1NS;
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}
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@ -965,6 +1190,11 @@ static void icc_igrpen_write(CPUARMState *env, const ARMCPRegInfo *ri,
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GICv3CPUState *cs = icc_cs_from_env(env);
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int grp = ri->opc2 & 1 ? GICV3_G1 : GICV3_G0;
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if (icv_access(env, grp == GICV3_G0 ? HCR_FMO : HCR_IMO)) {
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icv_igrpen_write(env, ri, value);
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return;
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}
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trace_gicv3_icc_igrpen_write(ri->opc2 & 1 ? 1 : 0,
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gicv3_redist_affid(cs), value);
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@ -1006,6 +1236,10 @@ static uint64_t icc_ctlr_el1_read(CPUARMState *env, const ARMCPRegInfo *ri)
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int bank = gicv3_use_ns_bank(env) ? GICV3_NS : GICV3_S;
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uint64_t value;
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if (icv_access(env, HCR_FMO | HCR_IMO)) {
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return icv_ctlr_read(env, ri);
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}
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value = cs->icc_ctlr_el1[bank];
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trace_gicv3_icc_ctlr_read(gicv3_redist_affid(cs), value);
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return value;
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@ -1018,6 +1252,11 @@ static void icc_ctlr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri,
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int bank = gicv3_use_ns_bank(env) ? GICV3_NS : GICV3_S;
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uint64_t mask;
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if (icv_access(env, HCR_FMO | HCR_IMO)) {
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icv_ctlr_write(env, ri, value);
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return;
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}
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trace_gicv3_icc_ctlr_write(gicv3_redist_affid(cs), value);
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/* Only CBPR and EOIMODE can be RW;
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@ -123,6 +123,16 @@ gicv3_ich_vtr_read(uint32_t cpu, uint64_t val) "GICv3 ICH_VTR read cpu %x value
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gicv3_ich_misr_read(uint32_t cpu, uint64_t val) "GICv3 ICH_MISR read cpu %x value 0x%" PRIx64
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gicv3_ich_eisr_read(uint32_t cpu, uint64_t val) "GICv3 ICH_EISR read cpu %x value 0x%" PRIx64
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gicv3_ich_elrsr_read(uint32_t cpu, uint64_t val) "GICv3 ICH_ELRSR read cpu %x value 0x%" PRIx64
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gicv3_icv_ap_read(int grp, int regno, uint32_t cpu, uint64_t val) "GICv3 ICV_AP%dR%d read cpu %x value 0x%" PRIx64
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gicv3_icv_ap_write(int grp, int regno, uint32_t cpu, uint64_t val) "GICv3 ICV_AP%dR%d write cpu %x value 0x%" PRIx64
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gicv3_icv_bpr_read(int grp, uint32_t cpu, uint64_t val) "GICv3 ICV_BPR%d read cpu %x value 0x%" PRIx64
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gicv3_icv_bpr_write(int grp, uint32_t cpu, uint64_t val) "GICv3 ICV_BPR%d write cpu %x value 0x%" PRIx64
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gicv3_icv_pmr_read(uint32_t cpu, uint64_t val) "GICv3 ICV_PMR read cpu %x value 0x%" PRIx64
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gicv3_icv_pmr_write(uint32_t cpu, uint64_t val) "GICv3 ICV_PMR write cpu %x value 0x%" PRIx64
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gicv3_icv_igrpen_read(int grp, uint32_t cpu, uint64_t val) "GICv3 ICV_IGRPEN%d read cpu %x value 0x%" PRIx64
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gicv3_icv_igrpen_write(int grp, uint32_t cpu, uint64_t val) "GICv3 ICV_IGRPEN%d write cpu %x value 0x%" PRIx64
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gicv3_icv_ctlr_read(uint32_t cpu, uint64_t val) "GICv3 ICV_CTLR read cpu %x value 0x%" PRIx64
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gicv3_icv_ctlr_write(uint32_t cpu, uint64_t val) "GICv3 ICV_CTLR write cpu %x value 0x%" PRIx64
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# hw/intc/arm_gicv3_dist.c
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gicv3_dist_read(uint64_t offset, uint64_t data, unsigned size, bool secure) "GICv3 distributor read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u secure %d"
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Reference in New Issue