PowerPC prep/chrp/pmac support
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@863 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
bellard
parent
a2a444d6e0
commit
77d4bc349a
300
hw/pci.c
300
hw/pci.c
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@ -470,6 +470,259 @@ void piix3_init(void)
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piix3_reset(d);
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}
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/* PREP pci init */
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static inline void set_config(PCIBridge *s, target_phys_addr_t addr)
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{
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int devfn, i;
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for(i = 0; i < 11; i++) {
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if ((addr & (1 << (11 + i))) != 0)
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break;
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}
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devfn = ((addr >> 8) & 7) | (i << 3);
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s->config_reg = 0x80000000 | (addr & 0xfc) | (devfn << 8);
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}
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static void PPC_PCIIO_writeb (target_phys_addr_t addr, uint32_t val)
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{
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PCIBridge *s = &pci_bridge;
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set_config(s, addr);
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pci_data_write(s, addr, val, 1);
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}
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static void PPC_PCIIO_writew (target_phys_addr_t addr, uint32_t val)
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{
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PCIBridge *s = &pci_bridge;
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set_config(s, addr);
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#ifdef TARGET_WORDS_BIGENDIAN
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val = bswap16(val);
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#endif
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pci_data_write(s, addr, val, 2);
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}
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static void PPC_PCIIO_writel (target_phys_addr_t addr, uint32_t val)
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{
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PCIBridge *s = &pci_bridge;
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set_config(s, addr);
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#ifdef TARGET_WORDS_BIGENDIAN
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val = bswap32(val);
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#endif
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pci_data_write(s, addr, val, 4);
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}
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static uint32_t PPC_PCIIO_readb (target_phys_addr_t addr)
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{
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PCIBridge *s = &pci_bridge;
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uint32_t val;
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set_config(s, addr);
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val = pci_data_read(s, addr, 1);
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return val;
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}
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static uint32_t PPC_PCIIO_readw (target_phys_addr_t addr)
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{
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PCIBridge *s = &pci_bridge;
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uint32_t val;
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set_config(s, addr);
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val = pci_data_read(s, addr, 2);
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#ifdef TARGET_WORDS_BIGENDIAN
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val = bswap16(val);
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#endif
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return val;
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}
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static uint32_t PPC_PCIIO_readl (target_phys_addr_t addr)
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{
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PCIBridge *s = &pci_bridge;
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uint32_t val;
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set_config(s, addr);
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val = pci_data_read(s, addr, 4);
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#ifdef TARGET_WORDS_BIGENDIAN
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val = bswap32(val);
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#endif
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return val;
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}
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static CPUWriteMemoryFunc *PPC_PCIIO_write[] = {
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&PPC_PCIIO_writeb,
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&PPC_PCIIO_writew,
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&PPC_PCIIO_writel,
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};
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static CPUReadMemoryFunc *PPC_PCIIO_read[] = {
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&PPC_PCIIO_readb,
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&PPC_PCIIO_readw,
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&PPC_PCIIO_readl,
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};
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void pci_prep_init(void)
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{
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PCIDevice *d;
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int PPC_io_memory;
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PPC_io_memory = cpu_register_io_memory(0, PPC_PCIIO_read, PPC_PCIIO_write);
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cpu_register_physical_memory(0x80800000, 0x00400000, PPC_io_memory);
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d = pci_register_device("PREP PCI Bridge", sizeof(PCIDevice), 0, 0,
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NULL, NULL);
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/* XXX: put correct IDs */
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d->config[0x00] = 0x11; // vendor_id
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d->config[0x01] = 0x10;
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d->config[0x02] = 0x26; // device_id
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d->config[0x03] = 0x00;
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d->config[0x08] = 0x02; // revision
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d->config[0x0a] = 0x04; // class_sub = pci2pci
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d->config[0x0b] = 0x06; // class_base = PCI_bridge
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d->config[0x0e] = 0x01; // header_type
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}
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/* pmac pci init */
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static void pci_pmac_config_writel (target_phys_addr_t addr, uint32_t val)
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{
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PCIBridge *s = &pci_bridge;
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#ifdef TARGET_WORDS_BIGENDIAN
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val = bswap32(val);
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#endif
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s->config_reg = val;
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}
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static uint32_t pci_pmac_config_readl (target_phys_addr_t addr)
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{
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PCIBridge *s = &pci_bridge;
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uint32_t val;
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val = s->config_reg;
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#ifdef TARGET_WORDS_BIGENDIAN
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val = bswap32(val);
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#endif
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return val;
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}
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static CPUWriteMemoryFunc *pci_pmac_config_write[] = {
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&pci_pmac_config_writel,
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&pci_pmac_config_writel,
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&pci_pmac_config_writel,
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};
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static CPUReadMemoryFunc *pci_pmac_config_read[] = {
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&pci_pmac_config_readl,
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&pci_pmac_config_readl,
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&pci_pmac_config_readl,
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};
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static void pci_pmac_writeb (target_phys_addr_t addr, uint32_t val)
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{
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PCIBridge *s = &pci_bridge;
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pci_data_write(s, addr, val, 1);
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}
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static void pci_pmac_writew (target_phys_addr_t addr, uint32_t val)
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{
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PCIBridge *s = &pci_bridge;
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#ifdef TARGET_WORDS_BIGENDIAN
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val = bswap16(val);
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#endif
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pci_data_write(s, addr, val, 2);
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}
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static void pci_pmac_writel (target_phys_addr_t addr, uint32_t val)
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{
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PCIBridge *s = &pci_bridge;
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#ifdef TARGET_WORDS_BIGENDIAN
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val = bswap32(val);
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#endif
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pci_data_write(s, addr, val, 4);
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}
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static uint32_t pci_pmac_readb (target_phys_addr_t addr)
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{
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PCIBridge *s = &pci_bridge;
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uint32_t val;
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val = pci_data_read(s, addr, 1);
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return val;
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}
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static uint32_t pci_pmac_readw (target_phys_addr_t addr)
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{
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PCIBridge *s = &pci_bridge;
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uint32_t val;
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val = pci_data_read(s, addr, 2);
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#ifdef TARGET_WORDS_BIGENDIAN
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val = bswap16(val);
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#endif
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return val;
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}
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static uint32_t pci_pmac_readl (target_phys_addr_t addr)
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{
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PCIBridge *s = &pci_bridge;
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uint32_t val;
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val = pci_data_read(s, addr, 4);
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#ifdef TARGET_WORDS_BIGENDIAN
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val = bswap32(val);
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#endif
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return val;
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}
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static CPUWriteMemoryFunc *pci_pmac_write[] = {
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&pci_pmac_writeb,
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&pci_pmac_writew,
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&pci_pmac_writel,
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};
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static CPUReadMemoryFunc *pci_pmac_read[] = {
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&pci_pmac_readb,
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&pci_pmac_readw,
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&pci_pmac_readl,
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};
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void pci_pmac_init(void)
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{
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PCIDevice *d;
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int pci_mem_config, pci_mem_data;
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pci_mem_config = cpu_register_io_memory(0, pci_pmac_config_read,
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pci_pmac_config_write);
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pci_mem_data = cpu_register_io_memory(0, pci_pmac_read, pci_pmac_write);
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cpu_register_physical_memory(0xfec00000, 0x1000, pci_mem_config);
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cpu_register_physical_memory(0xfee00000, 0x1000, pci_mem_data);
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d = pci_register_device("MPC106", sizeof(PCIDevice), 0, 0,
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NULL, NULL);
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/* same values as PearPC - check this */
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d->config[0x00] = 0x11; // vendor_id
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d->config[0x01] = 0x10;
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d->config[0x02] = 0x26; // device_id
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d->config[0x03] = 0x00;
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d->config[0x08] = 0x02; // revision
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d->config[0x0a] = 0x04; // class_sub = pci2pci
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d->config[0x0b] = 0x06; // class_base = PCI_bridge
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d->config[0x0e] = 0x01; // header_type
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d->config[0x18] = 0x0; // primary_bus
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d->config[0x19] = 0x1; // secondary_bus
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d->config[0x1a] = 0x1; // subordinate_bus
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d->config[0x1c] = 0x10; // io_base
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d->config[0x1d] = 0x20; // io_limit
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d->config[0x20] = 0x80; // memory_base
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d->config[0x21] = 0x80;
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d->config[0x22] = 0x90; // memory_limit
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d->config[0x23] = 0x80;
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d->config[0x24] = 0x00; // prefetchable_memory_base
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d->config[0x25] = 0x84;
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d->config[0x26] = 0x00; // prefetchable_memory_limit
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d->config[0x27] = 0x85;
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}
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/***********************************************************/
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/* generic PCI irq support */
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@ -484,6 +737,11 @@ static inline int pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num)
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}
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/* 0 <= irq_num <= 3. level must be 0 or 1 */
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#ifdef TARGET_PPC
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void pci_set_irq(PCIDevice *pci_dev, int irq_num, int level)
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{
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}
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#else
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void pci_set_irq(PCIDevice *pci_dev, int irq_num, int level)
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{
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int irq_index, shift, pic_irq, pic_level;
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@ -519,6 +777,7 @@ void pci_set_irq(PCIDevice *pci_dev, int irq_num, int level)
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pic_set_irq(pic_irq, pic_level);
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}
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}
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#endif
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/***********************************************************/
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/* monitor info on PCI */
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@ -780,3 +1039,44 @@ void pci_bios_init(void)
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}
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}
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}
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/*
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* This function initializes the PCI devices as a normal PCI BIOS
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* would do. It is provided just in case the BIOS has no support for
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* PCI.
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*/
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void pci_ppc_bios_init(void)
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{
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PCIBridge *s = &pci_bridge;
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PCIDevice **bus;
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int bus_num, devfn, i, irq;
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uint8_t elcr[2];
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pci_bios_io_addr = 0xc000;
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pci_bios_mem_addr = 0xc0000000;
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#if 0
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/* activate IRQ mappings */
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elcr[0] = 0x00;
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elcr[1] = 0x00;
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for(i = 0; i < 4; i++) {
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irq = pci_irqs[i];
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/* set to trigger level */
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elcr[irq >> 3] |= (1 << (irq & 7));
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/* activate irq remapping in PIIX */
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pci_config_writeb((PCIDevice *)piix3_state, 0x60 + i, irq);
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}
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isa_outb(elcr[0], 0x4d0);
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isa_outb(elcr[1], 0x4d1);
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#endif
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for(bus_num = 0; bus_num < 256; bus_num++) {
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bus = s->pci_bus[bus_num];
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if (bus) {
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for(devfn = 0; devfn < 256; devfn++) {
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if (bus[devfn])
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pci_bios_init_device(bus[devfn]);
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}
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}
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}
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}
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20
vl.c
20
vl.c
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@ -93,8 +93,11 @@ extern void __sigaction();
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#define PHYS_RAM_MAX_SIZE (2047 * 1024 * 1024)
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#endif
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#ifdef TARGET_PPC
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#define DEFAULT_RAM_SIZE 144
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#else
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#define DEFAULT_RAM_SIZE 32
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#endif
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/* in ms */
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#define GUI_REFRESH_INTERVAL 30
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@ -125,6 +128,7 @@ QEMUTimer *gui_timer;
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int vm_running;
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int audio_enabled = 0;
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int pci_enabled = 0;
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int prep_enabled = 0;
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/***********************************************************/
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/* x86 ISA bus support */
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@ -876,12 +880,17 @@ int serial_open_device(void)
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/* use console for serial port */
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return 0;
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} else {
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#if 0
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/* Not satisfying */
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if (openpty(&master_fd, &slave_fd, slave_name, NULL, NULL) < 0) {
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fprintf(stderr, "warning: could not create pseudo terminal for serial port\n");
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return -1;
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}
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fprintf(stderr, "Serial port redirected to %s\n", slave_name);
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return master_fd;
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#else
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return -1;
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#endif
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}
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}
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@ -2005,6 +2014,7 @@ enum {
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QEMU_OPTION_L,
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QEMU_OPTION_no_code_copy,
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QEMU_OPTION_pci,
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QEMU_OPTION_prep,
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};
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typedef struct QEMUOption {
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@ -2049,7 +2059,12 @@ const QEMUOption qemu_options[] = {
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{ "hdachs", HAS_ARG, QEMU_OPTION_hdachs },
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{ "L", HAS_ARG, QEMU_OPTION_L },
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{ "no-code-copy", 0, QEMU_OPTION_no_code_copy },
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/* temporary options */
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{ "pci", 0, QEMU_OPTION_pci },
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#ifdef TARGET_PPC
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{ "prep", 0, QEMU_OPTION_prep },
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#endif
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{ NULL },
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};
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@ -2323,6 +2338,9 @@ int main(int argc, char **argv)
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case QEMU_OPTION_pci:
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pci_enabled = 1;
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break;
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case QEMU_OPTION_prep:
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prep_enabled = 1;
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break;
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}
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}
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}
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22
vl.h
22
vl.h
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@ -429,6 +429,11 @@ void piix3_init(void);
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void pci_bios_init(void);
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void pci_info(void);
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/* temporary: will be moved in platform specific file */
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void pci_prep_init(void);
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void pci_pmac_init(void);
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void pci_ppc_bios_init(void);
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/* vga.c */
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#define VGA_RAM_SIZE (4096 * 1024)
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@ -580,6 +585,23 @@ void ppc_init (int ram_size, int vga_ram_size, int boot_device,
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DisplayState *ds, const char **fd_filename, int snapshot,
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const char *kernel_filename, const char *kernel_cmdline,
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const char *initrd_filename);
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void ppc_prep_init (int ram_size, int vga_ram_size, int boot_device,
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DisplayState *ds, const char **fd_filename, int snapshot,
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const char *kernel_filename, const char *kernel_cmdline,
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const char *initrd_filename);
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void ppc_chrp_init(int ram_size, int vga_ram_size, int boot_device,
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DisplayState *ds, const char **fd_filename, int snapshot,
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const char *kernel_filename, const char *kernel_cmdline,
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const char *initrd_filename);
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ppc_tb_t *cpu_ppc_tb_init (CPUPPCState *env, uint32_t freq);
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struct sysctrl_t;
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int prep_NVRAM_init (struct sysctrl_t *sysctrl, uint32_t RAM_size,
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uint32_t BIOS_size, int boot_device,
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uint32_t kernel_image);
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extern CPUWriteMemoryFunc *PPC_io_write[];
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extern CPUReadMemoryFunc *PPC_io_read[];
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extern int prep_enabled;
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/* monitor.c */
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void monitor_init(void);
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