target-arm: Store SPSR_EL1 state in banked_spsr[1] (SPSR_svc)
The AArch64 SPSR_EL1 register is architecturally mandated to be mapped to the AArch32 SPSR_svc register. This means its state should live in QEMU's env->banked_spsr[1] field. Correct the various places in the code that incorrectly put it in banked_spsr[0]. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -523,7 +523,7 @@ void aarch64_cpu_do_interrupt(CPUState *cs)
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aarch64_save_sp(env, arm_current_el(env));
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env->elr_el[new_el] = env->pc;
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} else {
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env->banked_spsr[0] = cpsr_read(env);
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env->banked_spsr[aarch64_banked_spsr_index(new_el)] = cpsr_read(env);
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if (!env->thumb) {
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env->cp15.esr_el[new_el] |= 1 << 25;
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}
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@ -2438,7 +2438,7 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
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{ .name = "SPSR_EL1", .state = ARM_CP_STATE_AA64,
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.type = ARM_CP_ALIAS,
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.opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 0,
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.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, banked_spsr[0]) },
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.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, banked_spsr[1]) },
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/* We rely on the access checks not allowing the guest to write to the
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* state field when SPSel indicates that it's being used as the stack
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* pointer.
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@ -82,11 +82,14 @@ static inline void arm_log_exception(int idx)
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/*
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* For AArch64, map a given EL to an index in the banked_spsr array.
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* Note that this mapping and the AArch32 mapping defined in bank_number()
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* must agree such that the AArch64<->AArch32 SPSRs have the architecturally
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* mandated mapping between each other.
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*/
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static inline unsigned int aarch64_banked_spsr_index(unsigned int el)
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{
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static const unsigned int map[4] = {
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[1] = 0, /* EL1. */
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[1] = 1, /* EL1. */
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[2] = 6, /* EL2. */
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[3] = 7, /* EL3. */
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};
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