target/arm: generalize 2-stage page-walk condition
The stage_1_mmu_idx() already effectively keeps track of which translation regimes have two stages. Don't hard-code another test. Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210112104511.36576-13-remi.denis.courmont@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -12160,11 +12160,11 @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
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target_ulong *page_size,
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target_ulong *page_size,
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ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs)
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ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs)
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{
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{
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if (mmu_idx == ARMMMUIdx_E10_0 ||
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ARMMMUIdx s1_mmu_idx = stage_1_mmu_idx(mmu_idx);
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mmu_idx == ARMMMUIdx_E10_1 ||
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mmu_idx == ARMMMUIdx_E10_1_PAN) {
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if (mmu_idx != s1_mmu_idx) {
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/* Call ourselves recursively to do the stage 1 and then stage 2
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/* Call ourselves recursively to do the stage 1 and then stage 2
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* translations.
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* translations if mmu_idx is a two-stage regime.
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*/
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*/
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if (arm_feature(env, ARM_FEATURE_EL2)) {
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if (arm_feature(env, ARM_FEATURE_EL2)) {
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hwaddr ipa;
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hwaddr ipa;
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@ -12172,9 +12172,8 @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
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int ret;
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int ret;
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ARMCacheAttrs cacheattrs2 = {};
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ARMCacheAttrs cacheattrs2 = {};
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ret = get_phys_addr(env, address, access_type,
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ret = get_phys_addr(env, address, access_type, s1_mmu_idx, &ipa,
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stage_1_mmu_idx(mmu_idx), &ipa, attrs,
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attrs, prot, page_size, fi, cacheattrs);
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prot, page_size, fi, cacheattrs);
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/* If S1 fails or S2 is disabled, return early. */
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/* If S1 fails or S2 is disabled, return early. */
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if (ret || regime_translation_disabled(env, ARMMMUIdx_Stage2)) {
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if (ret || regime_translation_disabled(env, ARMMMUIdx_Stage2)) {
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