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hw/riscv: boot: Remove compile time XLEN checks 

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Tested-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>
Message-id: 51e9842dbed1acceebad7f97bd3aae69aa1ac19e.1608142916.git.alistair.francis@wdc.com
This commit is contained in:
Alistair Francis 2020-12-16 10:22:37 -08:00
parent 09fe17125e
commit 7893677184
5 changed files with 39 additions and 31 deletions
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55
hw/riscv/boot.c
View File

@ -33,12 +33,6 @@
#include <libfdt.h> #include <libfdt.h>
#if defined(TARGET_RISCV32)
#define fw_dynamic_info_data(__val) cpu_to_le32(__val)
#else
#define fw_dynamic_info_data(__val) cpu_to_le64(__val)
#endif
bool riscv_is_32_bit(MachineState *machine) bool riscv_is_32_bit(MachineState *machine)
{ {
/* /*
@ -228,16 +222,24 @@ uint32_t riscv_load_fdt(hwaddr dram_base, uint64_t mem_size, void *fdt)
return fdt_addr; return fdt_addr;
} }
void riscv_rom_copy_firmware_info(hwaddr rom_base, hwaddr rom_size, void riscv_rom_copy_firmware_info(MachineState *machine, hwaddr rom_base,
uint32_t reset_vec_size, uint64_t kernel_entry) hwaddr rom_size, uint32_t reset_vec_size,
uint64_t kernel_entry)
{ {
struct fw_dynamic_info dinfo; struct fw_dynamic_info dinfo;
size_t dinfo_len; size_t dinfo_len;
dinfo.magic = fw_dynamic_info_data(FW_DYNAMIC_INFO_MAGIC_VALUE); if (sizeof(dinfo.magic) == 4) {
dinfo.version = fw_dynamic_info_data(FW_DYNAMIC_INFO_VERSION); dinfo.magic = cpu_to_le32(FW_DYNAMIC_INFO_MAGIC_VALUE);
dinfo.next_mode = fw_dynamic_info_data(FW_DYNAMIC_INFO_NEXT_MODE_S); dinfo.version = cpu_to_le32(FW_DYNAMIC_INFO_VERSION);
dinfo.next_addr = fw_dynamic_info_data(kernel_entry); dinfo.next_mode = cpu_to_le32(FW_DYNAMIC_INFO_NEXT_MODE_S);
dinfo.next_addr = cpu_to_le32(kernel_entry);
} else {
dinfo.magic = cpu_to_le64(FW_DYNAMIC_INFO_MAGIC_VALUE);
dinfo.version = cpu_to_le64(FW_DYNAMIC_INFO_VERSION);
dinfo.next_mode = cpu_to_le64(FW_DYNAMIC_INFO_NEXT_MODE_S);
dinfo.next_addr = cpu_to_le64(kernel_entry);
}
dinfo.options = 0; dinfo.options = 0;
dinfo.boot_hart = 0; dinfo.boot_hart = 0;
dinfo_len = sizeof(dinfo); dinfo_len = sizeof(dinfo);
@ -257,28 +259,24 @@ void riscv_rom_copy_firmware_info(hwaddr rom_base, hwaddr rom_size,
&address_space_memory); &address_space_memory);
} }
void riscv_setup_rom_reset_vec(hwaddr start_addr, hwaddr rom_base, void riscv_setup_rom_reset_vec(MachineState *machine, hwaddr start_addr,
hwaddr rom_size, uint64_t kernel_entry, hwaddr rom_base, hwaddr rom_size,
uint64_t kernel_entry,
uint32_t fdt_load_addr, void *fdt) uint32_t fdt_load_addr, void *fdt)
{ {
int i; int i;
uint32_t start_addr_hi32 = 0x00000000; uint32_t start_addr_hi32 = 0x00000000;
#if defined(TARGET_RISCV64) if (!riscv_is_32_bit(machine)) {
start_addr_hi32 = start_addr >> 32; start_addr_hi32 = start_addr >> 32;
#endif }
/* reset vector */ /* reset vector */
uint32_t reset_vec[10] = { uint32_t reset_vec[10] = {
0x00000297, /* 1: auipc t0, %pcrel_hi(fw_dyn) */ 0x00000297, /* 1: auipc t0, %pcrel_hi(fw_dyn) */
0x02828613, /* addi a2, t0, %pcrel_lo(1b) */ 0x02828613, /* addi a2, t0, %pcrel_lo(1b) */
0xf1402573, /* csrr a0, mhartid */ 0xf1402573, /* csrr a0, mhartid */
#if defined(TARGET_RISCV32) 0,
0x0202a583, /* lw a1, 32(t0) */ 0,
0x0182a283, /* lw t0, 24(t0) */
#elif defined(TARGET_RISCV64)
0x0202b583, /* ld a1, 32(t0) */
0x0182b283, /* ld t0, 24(t0) */
#endif
0x00028067, /* jr t0 */ 0x00028067, /* jr t0 */
start_addr, /* start: .dword */ start_addr, /* start: .dword */
start_addr_hi32, start_addr_hi32,
@ -286,6 +284,13 @@ void riscv_setup_rom_reset_vec(hwaddr start_addr, hwaddr rom_base,
0x00000000, 0x00000000,
/* fw_dyn: */ /* fw_dyn: */
}; };
if (riscv_is_32_bit(machine)) {
reset_vec[3] = 0x0202a583; /* lw a1, 32(t0) */
reset_vec[4] = 0x0182a283; /* lw t0, 24(t0) */
} else {
reset_vec[3] = 0x0202b583; /* ld a1, 32(t0) */
reset_vec[4] = 0x0182b283; /* ld t0, 24(t0) */
}
/* copy in the reset vector in little_endian byte order */ /* copy in the reset vector in little_endian byte order */
for (i = 0; i < ARRAY_SIZE(reset_vec); i++) { for (i = 0; i < ARRAY_SIZE(reset_vec); i++) {
@ -293,7 +298,7 @@ void riscv_setup_rom_reset_vec(hwaddr start_addr, hwaddr rom_base,
} }
rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
rom_base, &address_space_memory); rom_base, &address_space_memory);
riscv_rom_copy_firmware_info(rom_base, rom_size, sizeof(reset_vec), riscv_rom_copy_firmware_info(machine, rom_base, rom_size, sizeof(reset_vec),
kernel_entry); kernel_entry);
return; return;

2
hw/riscv/sifive_u.c
View File

@ -563,7 +563,7 @@ static void sifive_u_machine_init(MachineState *machine)
rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
memmap[SIFIVE_U_DEV_MROM].base, &address_space_memory); memmap[SIFIVE_U_DEV_MROM].base, &address_space_memory);
riscv_rom_copy_firmware_info(memmap[SIFIVE_U_DEV_MROM].base, riscv_rom_copy_firmware_info(machine, memmap[SIFIVE_U_DEV_MROM].base,
memmap[SIFIVE_U_DEV_MROM].size, memmap[SIFIVE_U_DEV_MROM].size,
sizeof(reset_vec), kernel_entry); sizeof(reset_vec), kernel_entry);
} }

3
hw/riscv/spike.c
View File

@ -296,7 +296,8 @@ static void spike_board_init(MachineState *machine)
fdt_load_addr = riscv_load_fdt(memmap[SPIKE_DRAM].base, fdt_load_addr = riscv_load_fdt(memmap[SPIKE_DRAM].base,
machine->ram_size, s->fdt); machine->ram_size, s->fdt);
/* load the reset vector */ /* load the reset vector */
riscv_setup_rom_reset_vec(memmap[SPIKE_DRAM].base, memmap[SPIKE_MROM].base, riscv_setup_rom_reset_vec(machine, memmap[SPIKE_DRAM].base,
memmap[SPIKE_MROM].base,
memmap[SPIKE_MROM].size, kernel_entry, memmap[SPIKE_MROM].size, kernel_entry,
fdt_load_addr, s->fdt); fdt_load_addr, s->fdt);

2
hw/riscv/virt.c
View File

@ -654,7 +654,7 @@ static void virt_machine_init(MachineState *machine)
fdt_load_addr = riscv_load_fdt(memmap[VIRT_DRAM].base, fdt_load_addr = riscv_load_fdt(memmap[VIRT_DRAM].base,
machine->ram_size, s->fdt); machine->ram_size, s->fdt);
/* load the reset vector */ /* load the reset vector */
riscv_setup_rom_reset_vec(start_addr, virt_memmap[VIRT_MROM].base, riscv_setup_rom_reset_vec(machine, start_addr, virt_memmap[VIRT_MROM].base,
virt_memmap[VIRT_MROM].size, kernel_entry, virt_memmap[VIRT_MROM].size, kernel_entry,
fdt_load_addr, s->fdt); fdt_load_addr, s->fdt);

8
include/hw/riscv/boot.h
View File

@ -41,10 +41,12 @@ target_ulong riscv_load_kernel(const char *kernel_filename,
hwaddr riscv_load_initrd(const char *filename, uint64_t mem_size, hwaddr riscv_load_initrd(const char *filename, uint64_t mem_size,
uint64_t kernel_entry, hwaddr *start); uint64_t kernel_entry, hwaddr *start);
uint32_t riscv_load_fdt(hwaddr dram_start, uint64_t dram_size, void *fdt); uint32_t riscv_load_fdt(hwaddr dram_start, uint64_t dram_size, void *fdt);
void riscv_setup_rom_reset_vec(hwaddr saddr, hwaddr rom_base, void riscv_setup_rom_reset_vec(MachineState *machine, hwaddr saddr,
hwaddr rom_size, uint64_t kernel_entry, hwaddr rom_base, hwaddr rom_size,
uint64_t kernel_entry,
uint32_t fdt_load_addr, void *fdt); uint32_t fdt_load_addr, void *fdt);
void riscv_rom_copy_firmware_info(hwaddr rom_base, hwaddr rom_size, void riscv_rom_copy_firmware_info(MachineState *machine, hwaddr rom_base,
hwaddr rom_size,
uint32_t reset_vec_size, uint32_t reset_vec_size,
uint64_t kernel_entry); uint64_t kernel_entry);