diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index c417f9dd52..e9bc97fee0 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -35,6 +35,7 @@ #include "sysemu/sysemu.h" #include "sysemu/hostmem.h" #include "sysemu/numa.h" +#include "sysemu/tcg.h" #include "sysemu/qtest.h" #include "sysemu/reset.h" #include "sysemu/runstate.h" diff --git a/hw/ppc/spapr_nested.c b/hw/ppc/spapr_nested.c index 936659b4c0..c02785756c 100644 --- a/hw/ppc/spapr_nested.c +++ b/hw/ppc/spapr_nested.c @@ -1511,7 +1511,7 @@ static target_ulong h_guest_getset_state(PowerPCCPU *cpu, if (flags & H_GUEST_GETSET_STATE_FLAG_GUEST_WIDE) { gsr.flags |= GUEST_STATE_REQUEST_GUEST_WIDE; } - if (flags & !H_GUEST_GETSET_STATE_FLAG_GUEST_WIDE) { + if (flags & ~H_GUEST_GETSET_STATE_FLAG_GUEST_WIDE) { return H_PARAMETER; /* flag not supported yet */ } diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 7e65f08147..22fdea093b 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -5820,7 +5820,7 @@ static void register_power10_dexcr_sprs(CPUPPCState *env) { spr_register(env, SPR_DEXCR, "DEXCR", SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic32, + &spr_read_generic, &spr_write_generic, 0); spr_register(env, SPR_UDEXCR, "UDEXCR", @@ -5831,7 +5831,7 @@ static void register_power10_dexcr_sprs(CPUPPCState *env) spr_register_hv(env, SPR_HDEXCR, "HDEXCR", SPR_NOACCESS, SPR_NOACCESS, SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic32, + &spr_read_generic, &spr_write_generic, 0); spr_register(env, SPR_UHDEXCR, "UHDEXCR", diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 80f584f933..674c05a2ce 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -1345,9 +1345,10 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp) * clear (e.g., see FWNMI in PAPR). */ new_msr |= (target_ulong)MSR_HVB; + + /* HV machine check exceptions don't have ME set */ + new_msr &= ~((target_ulong)1 << MSR_ME); } - /* machine check exceptions don't have ME set */ - new_msr &= ~((target_ulong)1 << MSR_ME); msr |= env->error_code; break; diff --git a/target/ppc/gdbstub.c b/target/ppc/gdbstub.c index 3f1e61bdb7..3b28d4e21c 100644 --- a/target/ppc/gdbstub.c +++ b/target/ppc/gdbstub.c @@ -305,6 +305,25 @@ static void gdb_gen_spr_feature(CPUState *cs) unsigned int num_regs = 0; int i; + for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) { + ppc_spr_t *spr = &env->spr_cb[i]; + + if (!spr->name) { + continue; + } + + /* + * GDB identifies registers based on the order they are + * presented in the XML. These ids will not match QEMU's + * representation (which follows the PowerISA). + * + * Store the position of the current register description so + * we can make the correspondence later. + */ + spr->gdb_id = num_regs; + num_regs++; + } + if (pcc->gdb_spr.xml) { return; } @@ -321,18 +340,8 @@ static void gdb_gen_spr_feature(CPUState *cs) } gdb_feature_builder_append_reg(&builder, g_ascii_strdown(spr->name, -1), - TARGET_LONG_BITS, num_regs, + TARGET_LONG_BITS, spr->gdb_id, "int", "spr"); - /* - * GDB identifies registers based on the order they are - * presented in the XML. These ids will not match QEMU's - * representation (which follows the PowerISA). - * - * Store the position of the current register description so - * we can make the correspondence later. - */ - spr->gdb_id = num_regs; - num_regs++; } gdb_feature_builder_end(&builder); diff --git a/target/ppc/mmu-radix64.c b/target/ppc/mmu-radix64.c index 5823e039e6..690dff7a49 100644 --- a/target/ppc/mmu-radix64.c +++ b/target/ppc/mmu-radix64.c @@ -300,8 +300,8 @@ static int ppc_radix64_next_level(AddressSpace *as, vaddr eaddr, if (nlb & mask) { qemu_log_mask(LOG_GUEST_ERROR, - "%s: misaligned page dir/table base: 0x"TARGET_FMT_lx - " page dir size: 0x"TARGET_FMT_lx"\n", + "%s: misaligned page dir/table base: 0x%" PRIx64 + " page dir size: 0x%" PRIx64 "\n", __func__, nlb, mask + 1); nlb &= ~mask; } @@ -324,8 +324,8 @@ static int ppc_radix64_walk_tree(AddressSpace *as, vaddr eaddr, if (base_addr & mask) { qemu_log_mask(LOG_GUEST_ERROR, - "%s: misaligned page dir base: 0x"TARGET_FMT_lx - " page dir size: 0x"TARGET_FMT_lx"\n", + "%s: misaligned page dir base: 0x%" PRIx64 + " page dir size: 0x%" PRIx64 "\n", __func__, base_addr, mask + 1); base_addr &= ~mask; } diff --git a/tests/avocado/ppc_hv_tests.py b/tests/avocado/ppc_hv_tests.py index 5080358e25..bf8822bb97 100644 --- a/tests/avocado/ppc_hv_tests.py +++ b/tests/avocado/ppc_hv_tests.py @@ -14,6 +14,7 @@ from avocado_qemu import wait_for_console_pattern, exec_command import os import time import subprocess +from datetime import datetime deps = ["xorriso"] # dependent tools needed in the test setup/box. @@ -42,10 +43,11 @@ def missing_deps(): # QEMU packages are downloaded and installed on each test. That's not a # large download, but it may be more polite to create qcow2 image with # QEMU already installed and use that. +# XXX: The order of these tests seems to matter, see git blame. +@skipIf(missing_deps(), 'dependencies (%s) not installed' % ','.join(deps)) @skipUnless(os.getenv('QEMU_TEST_FLAKY_TESTS'), 'Test sometimes gets stuck due to console handling problem') @skipUnless(os.getenv('AVOCADO_ALLOW_LARGE_STORAGE'), 'storage limited') @skipUnless(os.getenv('SPEED') == 'slow', 'runtime limited') -@skipIf(missing_deps(), 'dependencies (%s) not installed' % ','.join(deps)) class HypervisorTest(QemuSystemTest): timeout = 1000 @@ -106,6 +108,8 @@ class HypervisorTest(QemuSystemTest): exec_command(self, 'root') wait_for_console_pattern(self, 'localhost login:') wait_for_console_pattern(self, 'You may change this message by editing /etc/motd.') + # If the time is wrong, SSL certificates can fail. + exec_command(self, 'date -s "' + datetime.utcnow().strftime('%Y-%m-%d %H:%M:%S' + '"')) exec_command(self, 'setup-alpine -qe') wait_for_console_pattern(self, 'Updating repository indexes... done.')