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target/loongarch: Implement vext2xv

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This patch includes:
- VEXT2XV.{H/W/D}.B, VEXT2XV.{HU/WU/DU}.BU;
- VEXT2XV.{W/D}.B, VEXT2XV.{WU/DU}.HU;
- VEXT2XV.D.W, VEXT2XV.DU.WU.

Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230914022645.1151356-31-gaosong@loongson.cn>
This commit is contained in:
Song Gao 2023-09-14 10:26:18 +08:00
parent f0db0beb80
commit 790acb2a43
No known key found for this signature in database
GPG Key ID: 40A2FFF239263EDF
5 changed files with 80 additions and 0 deletions
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13
target/loongarch/disas.c
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@ -1997,6 +1997,19 @@ INSN_LASX(xvexth_wu_hu, vv)
INSN_LASX(xvexth_du_wu, vv)
INSN_LASX(xvexth_qu_du, vv)
INSN_LASX(vext2xv_h_b, vv)
INSN_LASX(vext2xv_w_b, vv)
INSN_LASX(vext2xv_d_b, vv)
INSN_LASX(vext2xv_w_h, vv)
INSN_LASX(vext2xv_d_h, vv)
INSN_LASX(vext2xv_d_w, vv)
INSN_LASX(vext2xv_hu_bu, vv)
INSN_LASX(vext2xv_wu_bu, vv)
INSN_LASX(vext2xv_du_bu, vv)
INSN_LASX(vext2xv_wu_hu, vv)
INSN_LASX(vext2xv_du_hu, vv)
INSN_LASX(vext2xv_du_wu, vv)
INSN_LASX(xvreplgr2vr_b, vr)
INSN_LASX(xvreplgr2vr_h, vr)
INSN_LASX(xvreplgr2vr_w, vr)

13
target/loongarch/helper.h
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@ -340,6 +340,19 @@ DEF_HELPER_FLAGS_3(vexth_wu_hu, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(vexth_du_wu, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(vexth_qu_du, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(vext2xv_h_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(vext2xv_w_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(vext2xv_d_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(vext2xv_w_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(vext2xv_d_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(vext2xv_d_w, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(vext2xv_hu_bu, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(vext2xv_wu_bu, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(vext2xv_du_bu, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(vext2xv_wu_hu, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(vext2xv_du_hu, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(vext2xv_du_wu, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vsigncov_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vsigncov_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(vsigncov_w, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)

13
target/loongarch/insn_trans/trans_vec.c.inc
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@ -3347,6 +3347,19 @@ TRANS(xvexth_wu_hu, LASX, gen_xx, gen_helper_vexth_wu_hu)
TRANS(xvexth_du_wu, LASX, gen_xx, gen_helper_vexth_du_wu)
TRANS(xvexth_qu_du, LASX, gen_xx, gen_helper_vexth_qu_du)
TRANS(vext2xv_h_b, LASX, gen_xx, gen_helper_vext2xv_h_b)
TRANS(vext2xv_w_b, LASX, gen_xx, gen_helper_vext2xv_w_b)
TRANS(vext2xv_d_b, LASX, gen_xx, gen_helper_vext2xv_d_b)
TRANS(vext2xv_w_h, LASX, gen_xx, gen_helper_vext2xv_w_h)
TRANS(vext2xv_d_h, LASX, gen_xx, gen_helper_vext2xv_d_h)
TRANS(vext2xv_d_w, LASX, gen_xx, gen_helper_vext2xv_d_w)
TRANS(vext2xv_hu_bu, LASX, gen_xx, gen_helper_vext2xv_hu_bu)
TRANS(vext2xv_wu_bu, LASX, gen_xx, gen_helper_vext2xv_wu_bu)
TRANS(vext2xv_du_bu, LASX, gen_xx, gen_helper_vext2xv_du_bu)
TRANS(vext2xv_wu_hu, LASX, gen_xx, gen_helper_vext2xv_wu_hu)
TRANS(vext2xv_du_hu, LASX, gen_xx, gen_helper_vext2xv_du_hu)
TRANS(vext2xv_du_wu, LASX, gen_xx, gen_helper_vext2xv_du_wu)
static void gen_vsigncov(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b)
{
TCGv_vec t1, zero;

13
target/loongarch/insns.decode
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@ -1580,6 +1580,19 @@ xvexth_wu_hu 0111 01101001 11101 11101 ..... ..... @vv
xvexth_du_wu 0111 01101001 11101 11110 ..... ..... @vv
xvexth_qu_du 0111 01101001 11101 11111 ..... ..... @vv
vext2xv_h_b 0111 01101001 11110 00100 ..... ..... @vv
vext2xv_w_b 0111 01101001 11110 00101 ..... ..... @vv
vext2xv_d_b 0111 01101001 11110 00110 ..... ..... @vv
vext2xv_w_h 0111 01101001 11110 00111 ..... ..... @vv
vext2xv_d_h 0111 01101001 11110 01000 ..... ..... @vv
vext2xv_d_w 0111 01101001 11110 01001 ..... ..... @vv
vext2xv_hu_bu 0111 01101001 11110 01010 ..... ..... @vv
vext2xv_wu_bu 0111 01101001 11110 01011 ..... ..... @vv
vext2xv_du_bu 0111 01101001 11110 01100 ..... ..... @vv
vext2xv_wu_hu 0111 01101001 11110 01101 ..... ..... @vv
vext2xv_du_hu 0111 01101001 11110 01110 ..... ..... @vv
vext2xv_du_wu 0111 01101001 11110 01111 ..... ..... @vv
xvreplgr2vr_b 0111 01101001 11110 00000 ..... ..... @vr
xvreplgr2vr_h 0111 01101001 11110 00001 ..... ..... @vr
xvreplgr2vr_w 0111 01101001 11110 00010 ..... ..... @vr

28
target/loongarch/vec_helper.c
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@ -763,6 +763,34 @@ VEXTH(vexth_hu_bu, 16, UH, UB)
VEXTH(vexth_wu_hu, 32, UW, UH)
VEXTH(vexth_du_wu, 64, UD, UW)
#define VEXT2XV(NAME, BIT, E1, E2) \
void HELPER(NAME)(void *vd, void *vj, uint32_t desc) \
{ \
int i; \
VReg temp = {}; \
VReg *Vd = (VReg *)vd; \
VReg *Vj = (VReg *)vj; \
int oprsz = simd_oprsz(desc); \
\
for (i = 0; i < oprsz / (BIT / 8); i++) { \
temp.E1(i) = Vj->E2(i); \
} \
*Vd = temp; \
}
VEXT2XV(vext2xv_h_b, 16, H, B)
VEXT2XV(vext2xv_w_b, 32, W, B)
VEXT2XV(vext2xv_d_b, 64, D, B)
VEXT2XV(vext2xv_w_h, 32, W, H)
VEXT2XV(vext2xv_d_h, 64, D, H)
VEXT2XV(vext2xv_d_w, 64, D, W)
VEXT2XV(vext2xv_hu_bu, 16, UH, UB)
VEXT2XV(vext2xv_wu_bu, 32, UW, UB)
VEXT2XV(vext2xv_du_bu, 64, UD, UB)
VEXT2XV(vext2xv_wu_hu, 32, UW, UH)
VEXT2XV(vext2xv_du_hu, 64, UD, UH)
VEXT2XV(vext2xv_du_wu, 64, UD, UW)
#define DO_SIGNCOV(a, b) (a == 0 ? 0 : a < 0 ? -b : b)
DO_3OP(vsigncov_b, 8, B, DO_SIGNCOV)