target/nios2: Prevent writes to read-only or reserved control fields
Create an array of masks which detail the writable and readonly bits for each control register. Apply them when writing to control registers, including the write to status during eret. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20220421151735.31996-38-richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson
parent
be77e1d5fe
commit
796945d596
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@ -102,6 +102,64 @@ static ObjectClass *nios2_cpu_class_by_name(const char *cpu_model)
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return object_class_by_name(TYPE_NIOS2_CPU);
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}
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static void realize_cr_status(CPUState *cs)
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{
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Nios2CPU *cpu = NIOS2_CPU(cs);
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/* Begin with all fields of all registers are reserved. */
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memset(cpu->cr_state, 0, sizeof(cpu->cr_state));
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/*
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* The combination of writable and readonly is the set of all
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* non-reserved fields. We apply writable as a mask to bits,
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* and merge in existing readonly bits, before storing.
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*/
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#define WR_REG(C) cpu->cr_state[C].writable = -1
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#define RO_REG(C) cpu->cr_state[C].readonly = -1
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#define WR_FIELD(C, F) cpu->cr_state[C].writable |= R_##C##_##F##_MASK
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#define RO_FIELD(C, F) cpu->cr_state[C].readonly |= R_##C##_##F##_MASK
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WR_FIELD(CR_STATUS, PIE);
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WR_REG(CR_ESTATUS);
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WR_REG(CR_BSTATUS);
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RO_REG(CR_CPUID);
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RO_REG(CR_EXCEPTION);
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WR_REG(CR_BADADDR);
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/* TODO: These control registers are not present with the EIC. */
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WR_REG(CR_IENABLE);
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RO_REG(CR_IPENDING);
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if (cpu->mmu_present) {
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WR_FIELD(CR_STATUS, U);
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WR_FIELD(CR_STATUS, EH);
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WR_FIELD(CR_PTEADDR, VPN);
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WR_FIELD(CR_PTEADDR, PTBASE);
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RO_FIELD(CR_TLBMISC, D);
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RO_FIELD(CR_TLBMISC, PERM);
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RO_FIELD(CR_TLBMISC, BAD);
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RO_FIELD(CR_TLBMISC, DBL);
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WR_FIELD(CR_TLBMISC, PID);
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WR_FIELD(CR_TLBMISC, WE);
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WR_FIELD(CR_TLBMISC, RD);
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WR_FIELD(CR_TLBMISC, WAY);
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WR_REG(CR_TLBACC);
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}
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/*
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* TODO: ECC (config, eccinj) and MPU (config, mpubase, mpuacc) are
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* unimplemented, so their corresponding control regs remain reserved.
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*/
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#undef WR_REG
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#undef RO_REG
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#undef WR_FIELD
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#undef RO_FIELD
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}
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static void nios2_cpu_realizefn(DeviceState *dev, Error **errp)
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{
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CPUState *cs = CPU(dev);
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@ -114,6 +172,7 @@ static void nios2_cpu_realizefn(DeviceState *dev, Error **errp)
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return;
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}
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realize_cr_status(cs);
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qemu_init_vcpu(cs);
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cpu_reset(cs);
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@ -147,23 +206,26 @@ static void nios2_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
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static int nios2_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
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{
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Nios2CPU *cpu = NIOS2_CPU(cs);
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CPUClass *cc = CPU_GET_CLASS(cs);
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CPUNios2State *env = &cpu->env;
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uint32_t val;
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if (n > cc->gdb_num_core_regs) {
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if (n < 32) { /* GP regs */
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val = env->regs[n];
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} else if (n == 32) { /* PC */
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val = env->pc;
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} else if (n < 49) { /* Status regs */
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unsigned cr = n - 33;
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if (nios2_cr_reserved(&cpu->cr_state[cr])) {
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val = 0;
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} else {
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val = env->ctrl[n - 33];
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}
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} else {
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/* Invalid regs */
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return 0;
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}
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if (n < 32) { /* GP regs */
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return gdb_get_reg32(mem_buf, env->regs[n]);
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} else if (n == 32) { /* PC */
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return gdb_get_reg32(mem_buf, env->pc);
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} else if (n < 49) { /* Status regs */
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return gdb_get_reg32(mem_buf, env->ctrl[n - 33]);
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}
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/* Invalid regs */
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return 0;
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return gdb_get_reg32(mem_buf, val);
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}
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static int nios2_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
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@ -171,17 +233,25 @@ static int nios2_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
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Nios2CPU *cpu = NIOS2_CPU(cs);
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CPUClass *cc = CPU_GET_CLASS(cs);
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CPUNios2State *env = &cpu->env;
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uint32_t val;
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if (n > cc->gdb_num_core_regs) {
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return 0;
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}
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val = ldl_p(mem_buf);
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if (n < 32) { /* GP regs */
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env->regs[n] = ldl_p(mem_buf);
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env->regs[n] = val;
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} else if (n == 32) { /* PC */
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env->pc = ldl_p(mem_buf);
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env->pc = val;
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} else if (n < 49) { /* Status regs */
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env->ctrl[n - 33] = ldl_p(mem_buf);
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unsigned cr = n - 33;
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/* ??? Maybe allow the debugger to write to readonly fields. */
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val &= cpu->cr_state[cr].writable;
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val |= cpu->cr_state[cr].readonly & env->ctrl[cr];
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env->ctrl[cr] = val;
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} else {
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g_assert_not_reached();
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}
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return 4;
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@ -190,6 +190,11 @@ struct CPUArchState {
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int error_code;
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};
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typedef struct {
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uint32_t writable;
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uint32_t readonly;
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} ControlRegState;
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/**
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* Nios2CPU:
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* @env: #CPUNios2State
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@ -213,9 +218,17 @@ struct ArchCPU {
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uint32_t reset_addr;
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uint32_t exception_addr;
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uint32_t fast_tlb_miss_addr;
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/* Bits within each control register which are reserved or readonly. */
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ControlRegState cr_state[NUM_CR_REGS];
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};
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static inline bool nios2_cr_reserved(const ControlRegState *s)
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{
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return (s->writable | s->readonly) == 0;
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}
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void nios2_tcg_init(void);
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void nios2_cpu_do_interrupt(CPUState *cs);
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void dump_mmu(CPUNios2State *env);
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@ -34,6 +34,15 @@ void helper_raise_exception(CPUNios2State *env, uint32_t index)
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#ifndef CONFIG_USER_ONLY
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void helper_eret(CPUNios2State *env, uint32_t new_status, uint32_t new_pc)
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{
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Nios2CPU *cpu = env_archcpu(env);
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/*
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* Both estatus and bstatus have no constraints on write;
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* do not allow reserved fields in status to be set.
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* TODO: more than this is required for shadow registers.
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*/
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new_status &= cpu->cr_state[CR_STATUS].writable;
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env->ctrl[CR_STATUS] = new_status;
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env->pc = new_pc;
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cpu_loop_exit(env_cpu(env));
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@ -102,6 +102,7 @@ typedef struct DisasContext {
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TCGv_i32 zero;
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target_ulong pc;
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int mem_idx;
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const ControlRegState *cr_state;
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} DisasContext;
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static TCGv cpu_R[NUM_GP_REGS];
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@ -471,17 +472,26 @@ static void callr(DisasContext *dc, uint32_t code, uint32_t flags)
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/* rC <- ctlN */
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static void rdctl(DisasContext *dc, uint32_t code, uint32_t flags)
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{
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R_TYPE(instr, code);
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TCGv t1, t2;
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if (!gen_check_supervisor(dc)) {
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return;
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}
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#ifdef CONFIG_USER_ONLY
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g_assert_not_reached();
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#else
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R_TYPE(instr, code);
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TCGv t1, t2;
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if (unlikely(instr.c == R_ZERO)) {
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return;
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}
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/* Reserved registers read as zero. */
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if (nios2_cr_reserved(&dc->cr_state[instr.imm5])) {
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tcg_gen_movi_tl(cpu_R[instr.c], 0);
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return;
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}
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switch (instr.imm5) {
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case CR_IPENDING:
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/*
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@ -505,6 +515,7 @@ static void rdctl(DisasContext *dc, uint32_t code, uint32_t flags)
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offsetof(CPUNios2State, ctrl[instr.imm5]));
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break;
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}
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#endif
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}
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/* ctlN <- rA */
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@ -519,6 +530,14 @@ static void wrctl(DisasContext *dc, uint32_t code, uint32_t flags)
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#else
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R_TYPE(instr, code);
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TCGv v = load_gpr(dc, instr.a);
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uint32_t ofs = offsetof(CPUNios2State, ctrl[instr.imm5]);
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uint32_t wr = dc->cr_state[instr.imm5].writable;
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uint32_t ro = dc->cr_state[instr.imm5].readonly;
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/* Skip reserved or readonly registers. */
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if (wr == 0) {
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return;
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}
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switch (instr.imm5) {
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case CR_PTEADDR:
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@ -530,17 +549,35 @@ static void wrctl(DisasContext *dc, uint32_t code, uint32_t flags)
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case CR_TLBMISC:
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gen_helper_mmu_write_tlbmisc(cpu_env, v);
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break;
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case CR_IPENDING:
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/* ipending is read only, writes ignored. */
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break;
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case CR_STATUS:
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case CR_IENABLE:
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/* If interrupts were enabled using WRCTL, trigger them. */
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dc->base.is_jmp = DISAS_UPDATE;
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/* fall through */
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default:
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tcg_gen_st_tl(v, cpu_env,
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offsetof(CPUNios2State, ctrl[instr.imm5]));
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if (wr == -1) {
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/* The register is entirely writable. */
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tcg_gen_st_tl(v, cpu_env, ofs);
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} else {
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/*
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* The register is partially read-only or reserved:
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* merge the value.
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*/
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TCGv n = tcg_temp_new();
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tcg_gen_andi_tl(n, v, wr);
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if (ro != 0) {
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TCGv o = tcg_temp_new();
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tcg_gen_ld_tl(o, cpu_env, ofs);
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tcg_gen_andi_tl(o, o, ro);
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tcg_gen_or_tl(n, n, o);
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tcg_temp_free(o);
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}
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tcg_gen_st_tl(n, cpu_env, ofs);
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tcg_temp_free(n);
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}
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break;
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}
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#endif
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@ -818,9 +855,11 @@ static void nios2_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
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{
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DisasContext *dc = container_of(dcbase, DisasContext, base);
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CPUNios2State *env = cs->env_ptr;
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Nios2CPU *cpu = env_archcpu(env);
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int page_insns;
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dc->mem_idx = cpu_mmu_index(env, false);
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dc->cr_state = cpu->cr_state;
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/* Bound the number of insns to execute to those left on the page. */
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page_insns = -(dc->base.pc_first | TARGET_PAGE_MASK) / 4;
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@ -932,16 +971,25 @@ void nios2_cpu_dump_state(CPUState *cs, FILE *f, int flags)
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}
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#if !defined(CONFIG_USER_ONLY)
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for (i = 0; i < NUM_CR_REGS; i++) {
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qemu_fprintf(f, "%9s=%8.8x ", cr_regnames[i], env->ctrl[i]);
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if ((i + 1) % 4 == 0) {
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qemu_fprintf(f, "\n");
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int j;
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for (i = j = 0; i < NUM_CR_REGS; i++) {
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if (!nios2_cr_reserved(&cpu->cr_state[i])) {
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qemu_fprintf(f, "%9s=%8.8x ", cr_regnames[i], env->ctrl[i]);
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if (++j % 4 == 0) {
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qemu_fprintf(f, "\n");
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}
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}
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}
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qemu_fprintf(f, " mmu write: VPN=%05X PID %02X TLBACC %08X\n",
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env->mmu.pteaddr_wr & R_CR_PTEADDR_VPN_MASK,
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FIELD_EX32(env->mmu.tlbmisc_wr, CR_TLBMISC, PID),
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env->mmu.tlbacc_wr);
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if (j % 4 != 0) {
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qemu_fprintf(f, "\n");
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}
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if (cpu->mmu_present) {
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qemu_fprintf(f, " mmu write: VPN=%05X PID %02X TLBACC %08X\n",
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env->mmu.pteaddr_wr & R_CR_PTEADDR_VPN_MASK,
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FIELD_EX32(env->mmu.tlbmisc_wr, CR_TLBMISC, PID),
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env->mmu.tlbacc_wr);
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}
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#endif
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qemu_fprintf(f, "\n\n");
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}
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