util: Merge cacheflush.c and cacheinfo.c
Combine the two files into cacheflush.c. There's a couple of bits that would be helpful to share between the two, and combining them seems better than exporting the bits. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20220621014837.189139-2-richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson
parent
418ade7849
commit
7971375287
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@ -1,5 +1,5 @@
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/*
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* Flush the host cpu caches.
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* Info about, and flushing the host cpu caches.
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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@ -9,8 +9,208 @@
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#include "qemu/cacheflush.h"
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#include "qemu/cacheinfo.h"
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#include "qemu/bitops.h"
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#include "qemu/host-utils.h"
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#include "qemu/atomic.h"
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int qemu_icache_linesize = 0;
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int qemu_icache_linesize_log;
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int qemu_dcache_linesize = 0;
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int qemu_dcache_linesize_log;
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/*
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* Operating system specific cache detection mechanisms.
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*/
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#if defined(_WIN32)
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static void sys_cache_info(int *isize, int *dsize)
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{
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SYSTEM_LOGICAL_PROCESSOR_INFORMATION *buf;
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DWORD size = 0;
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BOOL success;
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size_t i, n;
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/*
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* Check for the required buffer size first. Note that if the zero
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* size we use for the probe results in success, then there is no
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* data available; fail in that case.
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*/
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success = GetLogicalProcessorInformation(0, &size);
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if (success || GetLastError() != ERROR_INSUFFICIENT_BUFFER) {
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return;
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}
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n = size / sizeof(SYSTEM_LOGICAL_PROCESSOR_INFORMATION);
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size = n * sizeof(SYSTEM_LOGICAL_PROCESSOR_INFORMATION);
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buf = g_new0(SYSTEM_LOGICAL_PROCESSOR_INFORMATION, n);
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if (!GetLogicalProcessorInformation(buf, &size)) {
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goto fail;
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}
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for (i = 0; i < n; i++) {
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if (buf[i].Relationship == RelationCache
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&& buf[i].Cache.Level == 1) {
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switch (buf[i].Cache.Type) {
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case CacheUnified:
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*isize = *dsize = buf[i].Cache.LineSize;
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break;
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case CacheInstruction:
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*isize = buf[i].Cache.LineSize;
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break;
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case CacheData:
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*dsize = buf[i].Cache.LineSize;
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break;
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default:
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break;
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}
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}
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}
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fail:
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g_free(buf);
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}
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#elif defined(__APPLE__)
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# include <sys/sysctl.h>
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static void sys_cache_info(int *isize, int *dsize)
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{
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/* There's only a single sysctl for both I/D cache line sizes. */
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long size;
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size_t len = sizeof(size);
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if (!sysctlbyname("hw.cachelinesize", &size, &len, NULL, 0)) {
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*isize = *dsize = size;
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}
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}
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#elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__)
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# include <sys/sysctl.h>
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static void sys_cache_info(int *isize, int *dsize)
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{
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/* There's only a single sysctl for both I/D cache line sizes. */
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int size;
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size_t len = sizeof(size);
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if (!sysctlbyname("machdep.cacheline_size", &size, &len, NULL, 0)) {
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*isize = *dsize = size;
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}
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}
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#else
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/* POSIX */
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static void sys_cache_info(int *isize, int *dsize)
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{
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# ifdef _SC_LEVEL1_ICACHE_LINESIZE
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int tmp_isize = (int) sysconf(_SC_LEVEL1_ICACHE_LINESIZE);
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if (tmp_isize > 0) {
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*isize = tmp_isize;
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}
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# endif
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# ifdef _SC_LEVEL1_DCACHE_LINESIZE
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int tmp_dsize = (int) sysconf(_SC_LEVEL1_DCACHE_LINESIZE);
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if (tmp_dsize > 0) {
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*dsize = tmp_dsize;
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}
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# endif
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}
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#endif /* sys_cache_info */
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/*
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* Architecture (+ OS) specific cache detection mechanisms.
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*/
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#if defined(__aarch64__)
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static void arch_cache_info(int *isize, int *dsize)
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{
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if (*isize == 0 || *dsize == 0) {
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uint64_t ctr;
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/*
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* The real cache geometry is in CCSIDR_EL1/CLIDR_EL1/CSSELR_EL1,
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* but (at least under Linux) these are marked protected by the
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* kernel. However, CTR_EL0 contains the minimum linesize in the
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* entire hierarchy, and is used by userspace cache flushing.
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*/
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asm volatile("mrs\t%0, ctr_el0" : "=r"(ctr));
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if (*isize == 0) {
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*isize = 4 << (ctr & 0xf);
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}
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if (*dsize == 0) {
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*dsize = 4 << ((ctr >> 16) & 0xf);
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}
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}
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}
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#elif defined(_ARCH_PPC) && defined(__linux__)
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# include "elf.h"
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static void arch_cache_info(int *isize, int *dsize)
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{
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if (*isize == 0) {
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*isize = qemu_getauxval(AT_ICACHEBSIZE);
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}
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if (*dsize == 0) {
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*dsize = qemu_getauxval(AT_DCACHEBSIZE);
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}
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}
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#else
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static void arch_cache_info(int *isize, int *dsize) { }
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#endif /* arch_cache_info */
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/*
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* ... and if all else fails ...
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*/
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static void fallback_cache_info(int *isize, int *dsize)
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{
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/* If we can only find one of the two, assume they're the same. */
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if (*isize) {
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if (*dsize) {
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/* Success! */
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} else {
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*dsize = *isize;
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}
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} else if (*dsize) {
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*isize = *dsize;
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} else {
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#if defined(_ARCH_PPC)
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/*
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* For PPC, we're going to use the cache sizes computed for
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* flush_idcache_range. Which means that we must use the
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* architecture minimum.
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*/
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*isize = *dsize = 16;
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#else
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/* Otherwise, 64 bytes is not uncommon. */
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*isize = *dsize = 64;
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#endif
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}
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}
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static void __attribute__((constructor)) init_cache_info(void)
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{
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int isize = 0, dsize = 0;
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sys_cache_info(&isize, &dsize);
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arch_cache_info(&isize, &dsize);
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fallback_cache_info(&isize, &dsize);
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assert((isize & (isize - 1)) == 0);
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assert((dsize & (dsize - 1)) == 0);
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qemu_icache_linesize = isize;
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qemu_icache_linesize_log = ctz32(isize);
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qemu_dcache_linesize = dsize;
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qemu_dcache_linesize_log = ctz32(dsize);
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qatomic64_init();
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}
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/*
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* Architecture (+ OS) specific cache flushing mechanisms.
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*/
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#if defined(__i386__) || defined(__x86_64__) || defined(__s390__)
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/* Caches are coherent and do not require flushing; symbol inline. */
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200
util/cacheinfo.c
200
util/cacheinfo.c
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@ -1,200 +0,0 @@
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/*
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* cacheinfo.c - helpers to query the host about its caches
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*
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* Copyright (C) 2017, Emilio G. Cota <cota@braap.org>
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* License: GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*/
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#include "qemu/osdep.h"
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#include "qemu/host-utils.h"
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#include "qemu/atomic.h"
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#include "qemu/cacheinfo.h"
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int qemu_icache_linesize = 0;
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int qemu_icache_linesize_log;
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int qemu_dcache_linesize = 0;
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int qemu_dcache_linesize_log;
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/*
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* Operating system specific detection mechanisms.
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*/
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#if defined(_WIN32)
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static void sys_cache_info(int *isize, int *dsize)
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{
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SYSTEM_LOGICAL_PROCESSOR_INFORMATION *buf;
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DWORD size = 0;
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BOOL success;
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size_t i, n;
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/* Check for the required buffer size first. Note that if the zero
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size we use for the probe results in success, then there is no
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data available; fail in that case. */
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success = GetLogicalProcessorInformation(0, &size);
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if (success || GetLastError() != ERROR_INSUFFICIENT_BUFFER) {
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return;
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}
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n = size / sizeof(SYSTEM_LOGICAL_PROCESSOR_INFORMATION);
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size = n * sizeof(SYSTEM_LOGICAL_PROCESSOR_INFORMATION);
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buf = g_new0(SYSTEM_LOGICAL_PROCESSOR_INFORMATION, n);
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if (!GetLogicalProcessorInformation(buf, &size)) {
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goto fail;
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}
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for (i = 0; i < n; i++) {
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if (buf[i].Relationship == RelationCache
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&& buf[i].Cache.Level == 1) {
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switch (buf[i].Cache.Type) {
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case CacheUnified:
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*isize = *dsize = buf[i].Cache.LineSize;
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break;
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case CacheInstruction:
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*isize = buf[i].Cache.LineSize;
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break;
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case CacheData:
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*dsize = buf[i].Cache.LineSize;
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break;
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default:
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break;
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}
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}
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}
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fail:
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g_free(buf);
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}
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#elif defined(__APPLE__)
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# include <sys/sysctl.h>
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static void sys_cache_info(int *isize, int *dsize)
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{
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/* There's only a single sysctl for both I/D cache line sizes. */
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long size;
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size_t len = sizeof(size);
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if (!sysctlbyname("hw.cachelinesize", &size, &len, NULL, 0)) {
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*isize = *dsize = size;
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}
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}
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#elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__)
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# include <sys/sysctl.h>
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static void sys_cache_info(int *isize, int *dsize)
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{
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/* There's only a single sysctl for both I/D cache line sizes. */
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int size;
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size_t len = sizeof(size);
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if (!sysctlbyname("machdep.cacheline_size", &size, &len, NULL, 0)) {
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*isize = *dsize = size;
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}
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}
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#else
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/* POSIX */
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static void sys_cache_info(int *isize, int *dsize)
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{
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# ifdef _SC_LEVEL1_ICACHE_LINESIZE
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int tmp_isize = (int) sysconf(_SC_LEVEL1_ICACHE_LINESIZE);
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if (tmp_isize > 0) {
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*isize = tmp_isize;
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}
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# endif
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# ifdef _SC_LEVEL1_DCACHE_LINESIZE
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int tmp_dsize = (int) sysconf(_SC_LEVEL1_DCACHE_LINESIZE);
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if (tmp_dsize > 0) {
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*dsize = tmp_dsize;
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}
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# endif
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}
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#endif /* sys_cache_info */
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/*
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* Architecture (+ OS) specific detection mechanisms.
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*/
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#if defined(__aarch64__)
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static void arch_cache_info(int *isize, int *dsize)
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{
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if (*isize == 0 || *dsize == 0) {
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uint64_t ctr;
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/* The real cache geometry is in CCSIDR_EL1/CLIDR_EL1/CSSELR_EL1,
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but (at least under Linux) these are marked protected by the
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kernel. However, CTR_EL0 contains the minimum linesize in the
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entire hierarchy, and is used by userspace cache flushing. */
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asm volatile("mrs\t%0, ctr_el0" : "=r"(ctr));
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if (*isize == 0) {
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*isize = 4 << (ctr & 0xf);
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}
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if (*dsize == 0) {
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*dsize = 4 << ((ctr >> 16) & 0xf);
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}
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}
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}
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#elif defined(_ARCH_PPC) && defined(__linux__)
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# include "elf.h"
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static void arch_cache_info(int *isize, int *dsize)
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{
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if (*isize == 0) {
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*isize = qemu_getauxval(AT_ICACHEBSIZE);
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}
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if (*dsize == 0) {
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*dsize = qemu_getauxval(AT_DCACHEBSIZE);
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}
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}
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#else
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static void arch_cache_info(int *isize, int *dsize) { }
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#endif /* arch_cache_info */
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/*
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* ... and if all else fails ...
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*/
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static void fallback_cache_info(int *isize, int *dsize)
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{
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/* If we can only find one of the two, assume they're the same. */
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if (*isize) {
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if (*dsize) {
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/* Success! */
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} else {
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*dsize = *isize;
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}
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} else if (*dsize) {
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*isize = *dsize;
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} else {
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#if defined(_ARCH_PPC)
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/*
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* For PPC, we're going to use the cache sizes computed for
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* flush_idcache_range. Which means that we must use the
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* architecture minimum.
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*/
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*isize = *dsize = 16;
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#else
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/* Otherwise, 64 bytes is not uncommon. */
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*isize = *dsize = 64;
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#endif
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}
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}
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static void __attribute__((constructor)) init_cache_info(void)
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{
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int isize = 0, dsize = 0;
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sys_cache_info(&isize, &dsize);
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arch_cache_info(&isize, &dsize);
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fallback_cache_info(&isize, &dsize);
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assert((isize & (isize - 1)) == 0);
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assert((dsize & (dsize - 1)) == 0);
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qemu_icache_linesize = isize;
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qemu_icache_linesize_log = ctz32(isize);
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qemu_dcache_linesize = dsize;
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qemu_dcache_linesize_log = ctz32(dsize);
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qatomic64_init();
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}
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@ -27,7 +27,7 @@ util_ss.add(files('envlist.c', 'path.c', 'module.c'))
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util_ss.add(files('host-utils.c'))
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util_ss.add(files('bitmap.c', 'bitops.c'))
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util_ss.add(files('fifo8.c'))
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util_ss.add(files('cacheinfo.c', 'cacheflush.c'))
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util_ss.add(files('cacheflush.c'))
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util_ss.add(files('error.c', 'error-report.c'))
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util_ss.add(files('qemu-print.c'))
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util_ss.add(files('id.c'))
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