x86_64 and better i386 support
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4394 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
bellard
parent
b6f97c14f5
commit
798085733c
251
gdbstub.c
251
gdbstub.c
@ -240,112 +240,173 @@ static int put_packet(GDBState *s, char *buf)
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}
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#if defined(TARGET_I386)
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static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
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{
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int i, fpus;
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uint32_t *registers = (uint32_t *)mem_buf;
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#ifdef TARGET_X86_64
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/* This corresponds with amd64_register_info[] in gdb/amd64-tdep.c */
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uint64_t *registers64 = (uint64_t *)mem_buf;
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if (env->hflags & HF_CS64_MASK) {
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registers64[0] = tswap64(env->regs[R_EAX]);
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registers64[1] = tswap64(env->regs[R_EBX]);
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registers64[2] = tswap64(env->regs[R_ECX]);
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registers64[3] = tswap64(env->regs[R_EDX]);
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registers64[4] = tswap64(env->regs[R_ESI]);
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registers64[5] = tswap64(env->regs[R_EDI]);
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registers64[6] = tswap64(env->regs[R_EBP]);
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registers64[7] = tswap64(env->regs[R_ESP]);
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for(i = 8; i < 16; i++) {
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registers64[i] = tswap64(env->regs[i]);
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}
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registers64[16] = tswap64(env->eip);
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registers = (uint32_t *)®isters64[17];
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registers[0] = tswap32(env->eflags);
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registers[1] = tswap32(env->segs[R_CS].selector);
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registers[2] = tswap32(env->segs[R_SS].selector);
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registers[3] = tswap32(env->segs[R_DS].selector);
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registers[4] = tswap32(env->segs[R_ES].selector);
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registers[5] = tswap32(env->segs[R_FS].selector);
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registers[6] = tswap32(env->segs[R_GS].selector);
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/* XXX: convert floats */
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for(i = 0; i < 8; i++) {
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memcpy(mem_buf + 16 * 8 + 7 * 4 + i * 10, &env->fpregs[i], 10);
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}
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registers[27] = tswap32(env->fpuc); /* fctrl */
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fpus = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11;
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registers[28] = tswap32(fpus); /* fstat */
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registers[29] = 0; /* ftag */
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registers[30] = 0; /* fiseg */
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registers[31] = 0; /* fioff */
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registers[32] = 0; /* foseg */
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registers[33] = 0; /* fooff */
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registers[34] = 0; /* fop */
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for(i = 0; i < 16; i++) {
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memcpy(mem_buf + 16 * 8 + 35 * 4 + i * 16, &env->xmm_regs[i], 16);
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}
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registers[99] = tswap32(env->mxcsr);
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return 8 * 17 + 4 * 7 + 10 * 8 + 4 * 8 + 16 * 16 + 4;
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}
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static const uint8_t gdb_x86_64_regs[16] = {
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R_EAX, R_EBX, R_ECX, R_EDX, R_ESI, R_EDI, R_EBP, R_ESP,
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8, 9, 10, 11, 12, 13, 14, 15,
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};
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#endif
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for(i = 0; i < 8; i++) {
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registers[i] = env->regs[i];
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}
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registers[8] = env->eip;
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registers[9] = env->eflags;
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registers[10] = env->segs[R_CS].selector;
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registers[11] = env->segs[R_SS].selector;
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registers[12] = env->segs[R_DS].selector;
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registers[13] = env->segs[R_ES].selector;
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registers[14] = env->segs[R_FS].selector;
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registers[15] = env->segs[R_GS].selector;
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/* XXX: convert floats */
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for(i = 0; i < 8; i++) {
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memcpy(mem_buf + 16 * 4 + i * 10, &env->fpregs[i], 10);
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}
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registers[36] = env->fpuc;
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fpus = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11;
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registers[37] = fpus;
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registers[38] = 0; /* XXX: convert tags */
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registers[39] = 0; /* fiseg */
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registers[40] = 0; /* fioff */
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registers[41] = 0; /* foseg */
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registers[42] = 0; /* fooff */
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registers[43] = 0; /* fop */
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static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
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{
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int i, fpus, nb_regs;
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uint8_t *p;
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for(i = 0; i < 16; i++)
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tswapls(®isters[i]);
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for(i = 36; i < 44; i++)
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tswapls(®isters[i]);
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return 44 * 4;
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p = mem_buf;
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#ifdef TARGET_X86_64
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if (env->hflags & HF_CS64_MASK) {
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nb_regs = 16;
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for(i = 0; i < 16; i++) {
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*(uint64_t *)p = tswap64(env->regs[gdb_x86_64_regs[i]]);
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p += 8;
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}
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*(uint64_t *)p = tswap64(env->eip);
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p += 8;
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} else
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#endif
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{
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nb_regs = 8;
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for(i = 0; i < 8; i++) {
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*(uint32_t *)p = tswap32(env->regs[i]);
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p += 4;
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}
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*(uint32_t *)p = tswap32(env->eip);
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p += 4;
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}
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*(uint32_t *)p = tswap32(env->eflags);
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p += 4;
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*(uint32_t *)p = tswap32(env->segs[R_CS].selector);
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p += 4;
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*(uint32_t *)p = tswap32(env->segs[R_SS].selector);
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p += 4;
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*(uint32_t *)p = tswap32(env->segs[R_DS].selector);
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p += 4;
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*(uint32_t *)p = tswap32(env->segs[R_ES].selector);
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p += 4;
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*(uint32_t *)p = tswap32(env->segs[R_FS].selector);
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p += 4;
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*(uint32_t *)p = tswap32(env->segs[R_GS].selector);
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p += 4;
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for(i = 0; i < 8; i++) {
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/* XXX: convert floats */
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#ifdef USE_X86LDOUBLE
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memcpy(p, &env->fpregs[i], 10);
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#else
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memset(p, 0, 10);
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#endif
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p += 10;
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}
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*(uint32_t *)p = tswap32(env->fpuc); /* fctrl */
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p += 4;
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fpus = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11;
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*(uint32_t *)p = tswap32(fpus); /* fstat */
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p += 4;
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*(uint32_t *)p = 0; /* ftag */
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p += 4;
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*(uint32_t *)p = 0; /* fiseg */
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p += 4;
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*(uint32_t *)p = 0; /* fioff */
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p += 4;
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*(uint32_t *)p = 0; /* foseg */
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p += 4;
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*(uint32_t *)p = 0; /* fooff */
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p += 4;
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*(uint32_t *)p = 0; /* fop */
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p += 4;
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for(i = 0; i < nb_regs; i++) {
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*(uint64_t *)p = tswap64(env->xmm_regs[i].XMM_Q(0));
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p += 8;
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*(uint64_t *)p = tswap64(env->xmm_regs[i].XMM_Q(1));
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p += 8;
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}
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*(uint32_t *)p = tswap32(env->mxcsr);
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p += 4;
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return p - mem_buf;
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}
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static inline void cpu_gdb_load_seg(CPUState *env, const uint8_t **pp,
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int sreg)
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{
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const uint8_t *p;
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uint32_t sel;
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p = *pp;
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sel = tswap32(*(uint32_t *)p);
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p += 4;
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if (sel != env->segs[sreg].selector) {
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#if defined(CONFIG_USER_ONLY)
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cpu_x86_load_seg(env, sreg, sel);
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#else
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/* XXX: do it with a debug function which does not raise an
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exception */
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#endif
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}
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*pp = p;
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}
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static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
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{
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uint32_t *registers = (uint32_t *)mem_buf;
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int i;
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const uint8_t *p = mem_buf;
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int i, nb_regs;
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uint16_t fpus;
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for(i = 0; i < 8; i++) {
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env->regs[i] = tswapl(registers[i]);
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}
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env->eip = tswapl(registers[8]);
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env->eflags = tswapl(registers[9]);
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#if defined(CONFIG_USER_ONLY)
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#define LOAD_SEG(index, sreg)\
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if (tswapl(registers[index]) != env->segs[sreg].selector)\
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cpu_x86_load_seg(env, sreg, tswapl(registers[index]));
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LOAD_SEG(10, R_CS);
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LOAD_SEG(11, R_SS);
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LOAD_SEG(12, R_DS);
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LOAD_SEG(13, R_ES);
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LOAD_SEG(14, R_FS);
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LOAD_SEG(15, R_GS);
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#ifdef TARGET_X86_64
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if (env->hflags & HF_CS64_MASK) {
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nb_regs = 16;
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for(i = 0; i < 16; i++) {
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env->regs[gdb_x86_64_regs[i]] = tswap64(*(uint64_t *)p);
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p += 8;
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}
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env->eip = tswap64(*(uint64_t *)p);
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p += 8;
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} else
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#endif
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{
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nb_regs = 8;
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for(i = 0; i < 8; i++) {
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env->regs[i] = tswap32(*(uint32_t *)p);
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p += 4;
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}
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env->eip = tswap32(*(uint32_t *)p);
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p += 4;
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}
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env->eflags = tswap32(*(uint32_t *)p);
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p += 4;
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cpu_gdb_load_seg(env, &p, R_CS);
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cpu_gdb_load_seg(env, &p, R_SS);
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cpu_gdb_load_seg(env, &p, R_DS);
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cpu_gdb_load_seg(env, &p, R_ES);
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cpu_gdb_load_seg(env, &p, R_FS);
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cpu_gdb_load_seg(env, &p, R_GS);
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/* FPU state */
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for(i = 0; i < 8; i++) {
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/* XXX: convert floats */
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#ifdef USE_X86LDOUBLE
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memcpy(&env->fpregs[i], p, 10);
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#endif
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p += 10;
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}
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env->fpuc = tswap32(*(uint32_t *)p); /* fctrl */
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p += 4;
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fpus = tswap32(*(uint32_t *)p);
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p += 4;
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env->fpstt = (fpus >> 11) & 7;
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env->fpus = fpus & ~0x3800;
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p += 4 * 6;
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if (size >= ((p - mem_buf) + 16 * nb_regs + 4)) {
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/* SSE state */
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for(i = 0; i < nb_regs; i++) {
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env->xmm_regs[i].XMM_Q(0) = tswap64(*(uint64_t *)p);
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p += 8;
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env->xmm_regs[i].XMM_Q(1) = tswap64(*(uint64_t *)p);
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p += 8;
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}
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env->mxcsr = tswap32(*(uint32_t *)p);
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p += 4;
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}
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}
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#elif defined (TARGET_PPC)
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