target/xtensa: import de233_fpu core
de233_fpu is a variant of 233L core with double precision FPU. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
This commit is contained in:
Max Filippov
parent
6aa29c07ee
commit
79bc0fb5f1
58
target/xtensa/core-de233_fpu.c
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58
target/xtensa/core-de233_fpu.c
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@ -0,0 +1,58 @@
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/*
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* Copyright (c) 2020, Max Filippov, Open Source and Linux Lab.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of the Open Source and Linux Lab nor the
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* names of its contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "exec/gdbstub.h"
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#include "qemu-common.h"
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#include "qemu/host-utils.h"
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#include "core-de233_fpu/core-isa.h"
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#include "core-de233_fpu/core-matmap.h"
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#include "overlay_tool.h"
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#define xtensa_modules xtensa_modules_de233_fpu
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#include "core-de233_fpu/xtensa-modules.c.inc"
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static XtensaConfig de233_fpu __attribute__((unused)) = {
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.name = "de233_fpu",
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.gdb_regmap = {
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.reg = {
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#include "core-de233_fpu/gdb-config.c.inc"
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}
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},
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.isa_internal = &xtensa_modules,
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.clock_freq_khz = 40000,
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.opcode_translators = (const XtensaOpcodeTranslators *[]){
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&xtensa_core_opcodes,
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&xtensa_fpu_opcodes,
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NULL,
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},
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DEFAULT_SECTIONS
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};
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REGISTER_CORE(de233_fpu)
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727
target/xtensa/core-de233_fpu/core-isa.h
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727
target/xtensa/core-de233_fpu/core-isa.h
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/*
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* xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa
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* processor CORE configuration
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*
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* See <xtensa/config/core.h>, which includes this file, for more details.
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*/
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/* Xtensa processor core configuration information.
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Copyright (c) 1999-2020 Tensilica Inc.
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Permission is hereby granted, free of charge, to any person obtaining
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a copy of this software and associated documentation files (the
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"Software"), to deal in the Software without restriction, including
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without limitation the rights to use, copy, modify, merge, publish,
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distribute, sublicense, and/or sell copies of the Software, and to
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permit persons to whom the Software is furnished to do so, subject to
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the following conditions:
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The above copyright notice and this permission notice shall be included
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in all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
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CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
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#ifndef XTENSA_CORE_CONFIGURATION_H_
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#define XTENSA_CORE_CONFIGURATION_H_
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//depot/dev/Homewood/Xtensa/SWConfig/hal/core-common.h.tph#24 - edit change 444323 (text+ko)
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/****************************************************************************
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Parameters Useful for Any Code, USER or PRIVILEGED
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****************************************************************************/
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/*
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* Note: Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is
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* configured, and a value of 0 otherwise. These macros are always defined.
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*/
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/*----------------------------------------------------------------------
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ISA
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----------------------------------------------------------------------*/
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#define XCHAL_HAVE_BE 0 /* big-endian byte ordering */
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#define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */
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#define XCHAL_NUM_AREGS 32 /* num of physical addr regs */
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#define XCHAL_NUM_AREGS_LOG2 5 /* log2(XCHAL_NUM_AREGS) */
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#define XCHAL_MAX_INSTRUCTION_SIZE 3 /* max instr bytes (3..8) */
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#define XCHAL_HAVE_DEBUG 1 /* debug option */
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#define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */
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#define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */
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#define XCHAL_LOOP_BUFFER_SIZE 0 /* zero-ov. loop instr buffer size */
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#define XCHAL_HAVE_NSA 1 /* NSA/NSAU instructions */
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#define XCHAL_HAVE_MINMAX 1 /* MIN/MAX instructions */
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#define XCHAL_HAVE_SEXT 1 /* SEXT instruction */
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#define XCHAL_HAVE_DEPBITS 0 /* DEPBITS instruction */
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#define XCHAL_HAVE_CLAMPS 1 /* CLAMPS instruction */
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#define XCHAL_HAVE_MUL16 1 /* MUL16S/MUL16U instructions */
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#define XCHAL_HAVE_MUL32 1 /* MULL instruction */
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#define XCHAL_HAVE_MUL32_HIGH 0 /* MULUH/MULSH instructions */
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#define XCHAL_HAVE_DIV32 1 /* QUOS/QUOU/REMS/REMU instructions */
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#define XCHAL_HAVE_L32R 1 /* L32R instruction */
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#define XCHAL_HAVE_ABSOLUTE_LITERALS 0 /* non-PC-rel (extended) L32R */
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#define XCHAL_HAVE_CONST16 0 /* CONST16 instruction */
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#define XCHAL_HAVE_ADDX 1 /* ADDX#/SUBX# instructions */
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#define XCHAL_HAVE_EXCLUSIVE 0 /* L32EX/S32EX instructions */
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#define XCHAL_HAVE_WIDE_BRANCHES 0 /* B*.W18 or B*.W15 instr's */
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#define XCHAL_HAVE_PREDICTED_BRANCHES 0 /* B[EQ/EQZ/NE/NEZ]T instr's */
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#define XCHAL_HAVE_CALL4AND12 1 /* (obsolete option) */
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#define XCHAL_HAVE_ABS 1 /* ABS instruction */
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#define XCHAL_HAVE_RELEASE_SYNC 1 /* L32AI/S32RI instructions */
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#define XCHAL_HAVE_S32C1I 1 /* S32C1I instruction */
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#define XCHAL_HAVE_SPECULATION 0 /* speculation */
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#define XCHAL_HAVE_FULL_RESET 1 /* all regs/state reset */
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#define XCHAL_NUM_CONTEXTS 1 /* */
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#define XCHAL_NUM_MISC_REGS 2 /* num of scratch regs (0..4) */
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#define XCHAL_HAVE_TAP_MASTER 0 /* JTAG TAP control instr's */
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#define XCHAL_HAVE_PRID 1 /* processor ID register */
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#define XCHAL_HAVE_EXTERN_REGS 1 /* WER/RER instructions */
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#define XCHAL_HAVE_MX 0 /* MX core (Tensilica internal) */
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#define XCHAL_HAVE_MP_INTERRUPTS 0 /* interrupt distributor port */
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#define XCHAL_HAVE_MP_RUNSTALL 0 /* core RunStall control port */
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#define XCHAL_HAVE_PSO 0 /* Power Shut-Off */
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#define XCHAL_HAVE_PSO_CDM 0 /* core/debug/mem pwr domains */
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#define XCHAL_HAVE_PSO_FULL_RETENTION 0 /* all regs preserved on PSO */
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#define XCHAL_HAVE_THREADPTR 1 /* THREADPTR register */
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#define XCHAL_HAVE_BOOLEANS 1 /* boolean registers */
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#define XCHAL_HAVE_CP 1 /* CPENABLE reg (coprocessor) */
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#define XCHAL_CP_MAXCFG 8 /* max allowed cp id plus one */
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#define XCHAL_HAVE_MAC16 1 /* MAC16 package */
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#define XCHAL_HAVE_LX 1 /* LX core */
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#define XCHAL_HAVE_NX 0 /* NX core (starting RH) */
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#define XCHAL_HAVE_SUPERGATHER 0 /* SuperGather */
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#define XCHAL_HAVE_FUSION 0 /* Fusion*/
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#define XCHAL_HAVE_FUSION_FP 0 /* Fusion FP option */
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#define XCHAL_HAVE_FUSION_LOW_POWER 0 /* Fusion Low Power option */
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#define XCHAL_HAVE_FUSION_AES 0 /* Fusion BLE/Wifi AES-128 CCM option */
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#define XCHAL_HAVE_FUSION_CONVENC 0 /* Fusion Conv Encode option */
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#define XCHAL_HAVE_FUSION_LFSR_CRC 0 /* Fusion LFSR-CRC option */
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#define XCHAL_HAVE_FUSION_BITOPS 0 /* Fusion Bit Operations Support option */
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#define XCHAL_HAVE_FUSION_AVS 0 /* Fusion AVS option */
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#define XCHAL_HAVE_FUSION_16BIT_BASEBAND 0 /* Fusion 16-bit Baseband option */
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#define XCHAL_HAVE_FUSION_VITERBI 0 /* Fusion Viterbi option */
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#define XCHAL_HAVE_FUSION_SOFTDEMAP 0 /* Fusion Soft Bit Demap option */
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#define XCHAL_HAVE_HIFIPRO 0 /* HiFiPro Audio Engine pkg */
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#define XCHAL_HAVE_HIFI5 0 /* HiFi5 Audio Engine pkg */
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#define XCHAL_HAVE_HIFI5_NN_MAC 0 /* HiFi5 Audio Engine NN-MAC option */
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#define XCHAL_HAVE_HIFI5_VFPU 0 /* HiFi5 Audio Engine Single-Precision VFPU option */
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#define XCHAL_HAVE_HIFI5_HP_VFPU 0 /* HiFi5 Audio Engine Half-Precision VFPU option */
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#define XCHAL_HAVE_HIFI4 0 /* HiFi4 Audio Engine pkg */
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#define XCHAL_HAVE_HIFI4_VFPU 0 /* HiFi4 Audio Engine VFPU option */
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#define XCHAL_HAVE_HIFI3 0 /* HiFi3 Audio Engine pkg */
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#define XCHAL_HAVE_HIFI3_VFPU 0 /* HiFi3 Audio Engine VFPU option */
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#define XCHAL_HAVE_HIFI3Z 0 /* HiFi3Z Audio Engine pkg */
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#define XCHAL_HAVE_HIFI3Z_VFPU 0 /* HiFi3Z Audio Engine VFPU option */
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#define XCHAL_HAVE_HIFI2 0 /* HiFi2 Audio Engine pkg */
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#define XCHAL_HAVE_HIFI2EP 0 /* HiFi2EP */
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#define XCHAL_HAVE_HIFI_MINI 0
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#define XCHAL_HAVE_VECTORFPU2005 0 /* vector floating-point pkg */
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#define XCHAL_HAVE_USER_DPFPU 0 /* user DP floating-point pkg */
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#define XCHAL_HAVE_USER_SPFPU 0 /* user SP floating-point pkg */
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#define XCHAL_HAVE_FP 1 /* single prec floating point */
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#define XCHAL_HAVE_FP_DIV 1 /* FP with DIV instructions */
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#define XCHAL_HAVE_FP_RECIP 1 /* FP with RECIP instructions */
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#define XCHAL_HAVE_FP_SQRT 1 /* FP with SQRT instructions */
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#define XCHAL_HAVE_FP_RSQRT 1 /* FP with RSQRT instructions */
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#define XCHAL_HAVE_DFP 1 /* double precision FP pkg */
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#define XCHAL_HAVE_DFP_DIV 1 /* DFP with DIV instructions */
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#define XCHAL_HAVE_DFP_RECIP 1 /* DFP with RECIP instructions*/
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#define XCHAL_HAVE_DFP_SQRT 1 /* DFP with SQRT instructions */
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#define XCHAL_HAVE_DFP_RSQRT 1 /* DFP with RSQRT instructions*/
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#define XCHAL_HAVE_DFP_ACCEL 0 /* double precision FP acceleration pkg */
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#define XCHAL_HAVE_DFP_accel XCHAL_HAVE_DFP_ACCEL /* for backward compatibility */
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#define XCHAL_HAVE_DFPU_SINGLE_ONLY 0 /* DFPU Coprocessor, single precision only */
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#define XCHAL_HAVE_DFPU_SINGLE_DOUBLE 1 /* DFPU Coprocessor, single and double precision */
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#define XCHAL_HAVE_VECTRA1 0 /* Vectra I pkg */
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#define XCHAL_HAVE_VECTRALX 0 /* Vectra LX pkg */
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#define XCHAL_HAVE_FUSIONG 0 /* FusionG */
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#define XCHAL_HAVE_FUSIONG3 0 /* FusionG3 */
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#define XCHAL_HAVE_FUSIONG6 0 /* FusionG6 */
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#define XCHAL_HAVE_FUSIONG_SP_VFPU 0 /* sp_vfpu option on FusionG */
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#define XCHAL_HAVE_FUSIONG_DP_VFPU 0 /* dp_vfpu option on FusionG */
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#define XCHAL_FUSIONG_SIMD32 0 /* simd32 for FusionG */
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#define XCHAL_HAVE_FUSIONJ 0 /* FusionJ */
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#define XCHAL_HAVE_FUSIONJ6 0 /* FusionJ6 */
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#define XCHAL_HAVE_FUSIONJ_SP_VFPU 0 /* sp_vfpu option on FusionJ */
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#define XCHAL_HAVE_FUSIONJ_DP_VFPU 0 /* dp_vfpu option on FusionJ */
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#define XCHAL_FUSIONJ_SIMD32 0 /* simd32 for FusionJ */
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#define XCHAL_HAVE_PDX 0 /* PDX-LX */
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#define XCHAL_PDX_SIMD32 0 /* simd32 for PDX */
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#define XCHAL_HAVE_PDX4 0 /* PDX4-LX */
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#define XCHAL_HAVE_PDX8 0 /* PDX8-LX */
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#define XCHAL_HAVE_PDX16 0 /* PDX16-LX */
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#define XCHAL_HAVE_PDXNX 0 /* PDX-NX */
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#define XCHAL_HAVE_CONNXD2 0 /* ConnX D2 pkg */
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#define XCHAL_HAVE_CONNXD2_DUALLSFLIX 0 /* ConnX D2 & Dual LoadStore Flix */
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#define XCHAL_HAVE_BALL 0
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#define XCHAL_HAVE_BALLAP 0
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#define XCHAL_HAVE_BBE16 0 /* ConnX BBE16 pkg */
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#define XCHAL_HAVE_BBE16_RSQRT 0 /* BBE16 & vector recip sqrt */
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#define XCHAL_HAVE_BBE16_VECDIV 0 /* BBE16 & vector divide */
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#define XCHAL_HAVE_BBE16_DESPREAD 0 /* BBE16 & despread */
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#define XCHAL_HAVE_CONNX_B10 0 /* ConnX B10 pkg*/
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#define XCHAL_HAVE_CONNX_B20 0 /* ConnX B20 pkg*/
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#define XCHAL_HAVE_CONNX_B_SP_VFPU 0 /* Single-precision Vector Floating-point option on ConnX B10 & B20 */
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#define XCHAL_HAVE_CONNX_B_SPX_VFPU 0 /* Single-precision Extended Vector Floating-point option on ConnX B10 & B20 */
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#define XCHAL_HAVE_CONNX_B_HPX_VFPU 0 /* Half-precision Extended Vector Floating-point option on ConnX B10 & B20 */
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#define XCHAL_HAVE_CONNX_B_32B_MAC 0 /* 32-bit vector MAC (real and complex), FIR & FFT option on ConnX B10 & B20 */
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#define XCHAL_HAVE_CONNX_B_VITERBI 0 /* Viterbi option on ConnX B10 & B20 */
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#define XCHAL_HAVE_CONNX_B_TURBO 0 /* Turbo option on ConnX B10 & B20 */
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#define XCHAL_HAVE_CONNX_B_LDPC 0 /* LDPC option on ConnX B10 & B20 */
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#define XCHAL_HAVE_BBENEP 0 /* ConnX BBENEP pkgs */
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#define XCHAL_HAVE_BBENEP_SP_VFPU 0 /* sp_vfpu option on BBE-EP */
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#define XCHAL_HAVE_BSP3 0 /* ConnX BSP3 pkg */
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#define XCHAL_HAVE_BSP3_TRANSPOSE 0 /* BSP3 & transpose32x32 */
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#define XCHAL_HAVE_SSP16 0 /* ConnX SSP16 pkg */
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#define XCHAL_HAVE_SSP16_VITERBI 0 /* SSP16 & viterbi */
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#define XCHAL_HAVE_TURBO16 0 /* ConnX Turbo16 pkg */
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#define XCHAL_HAVE_BBP16 0 /* ConnX BBP16 pkg */
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#define XCHAL_HAVE_FLIX3 0 /* basic 3-way FLIX option */
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#define XCHAL_HAVE_GRIVPEP 0 /* General Release of IVPEP */
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#define XCHAL_HAVE_GRIVPEP_HISTOGRAM 0 /* Histogram option on GRIVPEP */
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#define XCHAL_HAVE_VISION 0 /* Vision P5/P6 */
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#define XCHAL_VISION_SIMD16 0 /* simd16 for Vision P5/P6 */
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#define XCHAL_VISION_TYPE 0 /* Vision P5, P6, Q6 or Q7 */
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#define XCHAL_VISION_QUAD_MAC_TYPE 0 /* quad_mac option on Vision P6 */
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#define XCHAL_HAVE_VISION_HISTOGRAM 0 /* histogram option on Vision P5/P6 */
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#define XCHAL_HAVE_VISION_SP_VFPU 0 /* sp_vfpu option on Vision P5/P6/Q6/Q7 */
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#define XCHAL_HAVE_VISION_SP_VFPU_2XFMAC 0 /* sp_vfpu_2xfma option on Vision Q7 */
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#define XCHAL_HAVE_VISION_HP_VFPU 0 /* hp_vfpu option on Vision P6/Q6 */
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#define XCHAL_HAVE_VISION_HP_VFPU_2XFMAC 0 /* hp_vfpu_2xfma option on Vision Q7 */
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#define XCHAL_HAVE_VISIONC 0 /* Vision C */
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#define XCHAL_HAVE_XNNE 0 /* XNNE */
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/*----------------------------------------------------------------------
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MISC
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----------------------------------------------------------------------*/
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#define XCHAL_NUM_LOADSTORE_UNITS 1 /* load/store units */
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#define XCHAL_NUM_WRITEBUFFER_ENTRIES 8 /* size of write buffer */
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#define XCHAL_INST_FETCH_WIDTH 4 /* instr-fetch width in bytes */
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#define XCHAL_DATA_WIDTH 8 /* data width in bytes */
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#define XCHAL_DATA_PIPE_DELAY 1 /* d-side pipeline delay
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(1 = 5-stage, 2 = 7-stage) */
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#define XCHAL_CLOCK_GATING_GLOBAL 1 /* global clock gating */
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#define XCHAL_CLOCK_GATING_FUNCUNIT 1 /* funct. unit clock gating */
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/* In T1050, applies to selected core load and store instructions (see ISA): */
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#define XCHAL_UNALIGNED_LOAD_EXCEPTION 1 /* unaligned loads cause exc. */
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#define XCHAL_UNALIGNED_STORE_EXCEPTION 1 /* unaligned stores cause exc.*/
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#define XCHAL_UNALIGNED_LOAD_HW 0 /* unaligned loads work in hw */
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#define XCHAL_UNALIGNED_STORE_HW 0 /* unaligned stores work in hw*/
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#define XCHAL_UNIFIED_LOADSTORE 0
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#define XCHAL_SW_VERSION 1403000 /* sw version of this header */
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#define XCHAL_SW_VERSION_MAJOR 14000 /* major ver# of sw */
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#define XCHAL_SW_VERSION_MINOR 3 /* minor ver# of sw */
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#define XCHAL_SW_VERSION_MICRO 0 /* micro ver# of sw */
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#define XCHAL_SW_MINOR_VERSION 1403000 /* with zeroed micro */
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#define XCHAL_SW_MICRO_VERSION 1403000
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#define XCHAL_CORE_ID "DE_233L_FPU" /* alphanum core name
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(CoreID) set in the Xtensa
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Processor Generator */
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#define XCHAL_BUILD_UNIQUE_ID 0x000872E0 /* 22-bit sw build ID */
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/*
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* These definitions describe the hardware targeted by this software.
|
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*/
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#define XCHAL_HW_CONFIGID0 0xC1039286 /* ConfigID hi 32 bits*/
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#define XCHAL_HW_CONFIGID1 0x28C872E0 /* ConfigID lo 32 bits*/
|
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#define XCHAL_HW_VERSION_NAME "LX7.1.3" /* full version name */
|
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#define XCHAL_HW_VERSION_MAJOR 2810 /* major ver# of targeted hw */
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#define XCHAL_HW_VERSION_MINOR 3 /* minor ver# of targeted hw */
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#define XCHAL_HW_VERSION_MICRO 0 /* subdot ver# of targeted hw */
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#define XCHAL_HW_VERSION 281030 /* major*100+(major<2810 ? minor : minor*10+micro) */
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#define XCHAL_HW_REL_LX7 1
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#define XCHAL_HW_REL_LX7_1 1
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#define XCHAL_HW_REL_LX7_1_3 1
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#define XCHAL_HW_CONFIGID_RELIABLE 1
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||||
/* If software targets a *range* of hardware versions, these are the bounds: */
|
||||
#define XCHAL_HW_MIN_VERSION_MAJOR 2810 /* major v of earliest tgt hw */
|
||||
#define XCHAL_HW_MIN_VERSION_MINOR 3 /* minor v of earliest tgt hw */
|
||||
#define XCHAL_HW_MIN_VERSION_MICRO 0 /* micro v of earliest tgt hw */
|
||||
#define XCHAL_HW_MIN_VERSION 281030 /* earliest targeted hw */
|
||||
#define XCHAL_HW_MAX_VERSION_MAJOR 2810 /* major v of latest tgt hw */
|
||||
#define XCHAL_HW_MAX_VERSION_MINOR 3 /* minor v of latest tgt hw */
|
||||
#define XCHAL_HW_MAX_VERSION_MICRO 0 /* micro v of latest tgt hw */
|
||||
#define XCHAL_HW_MAX_VERSION 281030 /* latest targeted hw */
|
||||
|
||||
/* Config is enabled for functional safety: */
|
||||
#define XCHAL_HAVE_FUNC_SAFETY 0
|
||||
|
||||
#define XCHAL_HAVE_APB 0
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
CACHE
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
#define XCHAL_ICACHE_LINESIZE 32 /* I-cache line size in bytes */
|
||||
#define XCHAL_DCACHE_LINESIZE 32 /* D-cache line size in bytes */
|
||||
#define XCHAL_ICACHE_LINEWIDTH 5 /* log2(I line size in bytes) */
|
||||
#define XCHAL_DCACHE_LINEWIDTH 5 /* log2(D line size in bytes) */
|
||||
|
||||
#define XCHAL_ICACHE_SIZE 16384 /* I-cache size in bytes or 0 */
|
||||
#define XCHAL_ICACHE_SIZE_LOG2 14
|
||||
#define XCHAL_DCACHE_SIZE 16384 /* D-cache size in bytes or 0 */
|
||||
#define XCHAL_DCACHE_SIZE_LOG2 14
|
||||
|
||||
#define XCHAL_DCACHE_IS_WRITEBACK 1 /* writeback feature */
|
||||
#define XCHAL_DCACHE_IS_COHERENT 0 /* MP coherence feature */
|
||||
|
||||
#define XCHAL_HAVE_PREFETCH 0 /* PREFCTL register */
|
||||
#define XCHAL_HAVE_PREFETCH_L1 0 /* prefetch to L1 cache */
|
||||
#define XCHAL_PREFETCH_CASTOUT_LINES 0 /* dcache pref. castout bufsz */
|
||||
#define XCHAL_PREFETCH_ENTRIES 0 /* cache prefetch entries */
|
||||
#define XCHAL_PREFETCH_BLOCK_ENTRIES 0 /* prefetch block streams */
|
||||
#define XCHAL_HAVE_CACHE_BLOCKOPS 0 /* block prefetch for caches */
|
||||
#define XCHAL_HAVE_CME_DOWNGRADES 0
|
||||
#define XCHAL_HAVE_ICACHE_TEST 1 /* Icache test instructions */
|
||||
#define XCHAL_HAVE_DCACHE_TEST 1 /* Dcache test instructions */
|
||||
#define XCHAL_HAVE_ICACHE_DYN_WAYS 0 /* Icache dynamic way support */
|
||||
#define XCHAL_HAVE_DCACHE_DYN_WAYS 0 /* Dcache dynamic way support */
|
||||
#define XCHAL_HAVE_ICACHE_DYN_ENABLE 0 /* Icache enabled via MEMCTL */
|
||||
#define XCHAL_HAVE_DCACHE_DYN_ENABLE 0 /* Dcache enabled via MEMCTL */
|
||||
|
||||
#define XCHAL_L1SCACHE_SIZE 0
|
||||
#define XCHAL_L1SCACHE_SIZE_LOG2 0
|
||||
#define XCHAL_L1SCACHE_WAYS 1
|
||||
#define XCHAL_L1SCACHE_WAYS_LOG2 0
|
||||
#define XCHAL_L1SCACHE_ACCESS_SIZE 0
|
||||
#define XCHAL_L1SCACHE_BANKS 1
|
||||
|
||||
#define XCHAL_HAVE_L2 0 /* NX L2 cache controller */
|
||||
|
||||
/* Number of cores in cluster */
|
||||
#if XCHAL_HAVE_L2
|
||||
#define XCHAL_NUM_CORES_IN_CLUSTER XCHAL_L2CC_NUM_CORES_LOG2
|
||||
#else
|
||||
#define XCHAL_NUM_CORES_IN_CLUSTER 0
|
||||
#endif
|
||||
|
||||
/* PRID_ID macros are for internal use only ... subject to removal */
|
||||
#define PRID_ID_SHIFT 0
|
||||
#define PRID_ID_BITS 4
|
||||
#define PRID_ID_MASK 0x0000000F
|
||||
|
||||
/* This one is a form of caching, though not architecturally visible: */
|
||||
#define XCHAL_HAVE_BRANCH_PREDICTION 0 /* branch [target] prediction */
|
||||
|
||||
|
||||
|
||||
|
||||
/****************************************************************************
|
||||
Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code
|
||||
****************************************************************************/
|
||||
|
||||
|
||||
#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
CACHE
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
#define XCHAL_HAVE_PIF 1 /* any outbound bus present */
|
||||
|
||||
#define XCHAL_HAVE_AXI 0 /* AXI bus */
|
||||
#define XCHAL_HAVE_AXI_ECC 0 /* ECC on AXI bus */
|
||||
#define XCHAL_HAVE_ACELITE 0 /* ACELite bus */
|
||||
|
||||
#define XCHAL_HAVE_PIF_WR_RESP 0 /* pif write response */
|
||||
#define XCHAL_HAVE_PIF_REQ_ATTR 0 /* pif attribute */
|
||||
|
||||
/* If present, cache size in bytes == (ways * 2^(linewidth + setwidth)). */
|
||||
|
||||
/* Number of cache sets in log2(lines per way): */
|
||||
#define XCHAL_ICACHE_SETWIDTH 7
|
||||
#define XCHAL_DCACHE_SETWIDTH 7
|
||||
|
||||
/* Cache set associativity (number of ways): */
|
||||
#define XCHAL_ICACHE_WAYS 4
|
||||
#define XCHAL_ICACHE_WAYS_LOG2 2
|
||||
#define XCHAL_DCACHE_WAYS 4
|
||||
#define XCHAL_DCACHE_WAYS_LOG2 2
|
||||
|
||||
/* Cache features: */
|
||||
#define XCHAL_ICACHE_LINE_LOCKABLE 1
|
||||
#define XCHAL_DCACHE_LINE_LOCKABLE 1
|
||||
#define XCHAL_ICACHE_ECC_PARITY 0
|
||||
#define XCHAL_DCACHE_ECC_PARITY 0
|
||||
#define XCHAL_ICACHE_ECC_WIDTH 4
|
||||
#define XCHAL_DCACHE_ECC_WIDTH 1
|
||||
|
||||
/* Cache access size in bytes (affects operation of SICW instruction): */
|
||||
#define XCHAL_ICACHE_ACCESS_SIZE 4
|
||||
#define XCHAL_DCACHE_ACCESS_SIZE 8
|
||||
|
||||
#define XCHAL_DCACHE_BANKS 1 /* number of banks */
|
||||
|
||||
/* The number of Cache lines associated with a single cache tag */
|
||||
#define XCHAL_DCACHE_LINES_PER_TAG_LOG2 0
|
||||
|
||||
/* Number of encoded cache attr bits (see <xtensa/hal.h> for decoded bits): */
|
||||
#define XCHAL_CA_BITS 4
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
INTERNAL I/D RAM/ROMs and XLMI
|
||||
----------------------------------------------------------------------*/
|
||||
#define XCHAL_NUM_INSTROM 0 /* number of core instr. ROMs */
|
||||
#define XCHAL_NUM_INSTRAM 0 /* number of core instr. RAMs */
|
||||
#define XCHAL_NUM_DATAROM 0 /* number of core data ROMs */
|
||||
#define XCHAL_NUM_DATARAM 0 /* number of core data RAMs */
|
||||
#define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/
|
||||
#define XCHAL_NUM_XLMI 0 /* number of core XLMI ports */
|
||||
#define XCHAL_HAVE_IRAMCFG 0 /* IRAMxCFG register present */
|
||||
#define XCHAL_HAVE_DRAMCFG 0 /* DRAMxCFG register present */
|
||||
|
||||
|
||||
#define XCHAL_HAVE_IDMA 0
|
||||
|
||||
|
||||
#define XCHAL_HAVE_IMEM_LOADSTORE 1 /* can load/store to IROM/IRAM*/
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
INTERRUPTS and TIMERS
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
#define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */
|
||||
#define XCHAL_HAVE_NMI 1 /* non-maskable interrupt */
|
||||
#define XCHAL_HAVE_CCOUNT 1 /* CCOUNT reg. (timer option) */
|
||||
#define XCHAL_NUM_TIMERS 3 /* number of CCOMPAREn regs */
|
||||
#define XCHAL_NUM_INTERRUPTS 22 /* number of interrupts */
|
||||
#define XCHAL_NUM_INTERRUPTS_LOG2 5 /* ceil(log2(NUM_INTERRUPTS)) */
|
||||
#define XCHAL_NUM_EXTINTERRUPTS 17 /* num of external interrupts */
|
||||
#define XCHAL_NUM_INTLEVELS 6 /* number of interrupt levels
|
||||
(not including level zero) */
|
||||
|
||||
|
||||
#define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* med/high-pri. interrupts */
|
||||
#define XCHAL_EXCM_LEVEL 3 /* level masked by PS.EXCM */
|
||||
/* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */
|
||||
|
||||
/* Masks of interrupts at each interrupt level: */
|
||||
#define XCHAL_INTLEVEL1_MASK 0x001F80FF
|
||||
#define XCHAL_INTLEVEL2_MASK 0x00000100
|
||||
#define XCHAL_INTLEVEL3_MASK 0x00200E00
|
||||
#define XCHAL_INTLEVEL4_MASK 0x00001000
|
||||
#define XCHAL_INTLEVEL5_MASK 0x00002000
|
||||
#define XCHAL_INTLEVEL6_MASK 0x00000000
|
||||
#define XCHAL_INTLEVEL7_MASK 0x00004000
|
||||
|
||||
/* Masks of interrupts at each range 1..n of interrupt levels: */
|
||||
#define XCHAL_INTLEVEL1_ANDBELOW_MASK 0x001F80FF
|
||||
#define XCHAL_INTLEVEL2_ANDBELOW_MASK 0x001F81FF
|
||||
#define XCHAL_INTLEVEL3_ANDBELOW_MASK 0x003F8FFF
|
||||
#define XCHAL_INTLEVEL4_ANDBELOW_MASK 0x003F9FFF
|
||||
#define XCHAL_INTLEVEL5_ANDBELOW_MASK 0x003FBFFF
|
||||
#define XCHAL_INTLEVEL6_ANDBELOW_MASK 0x003FBFFF
|
||||
#define XCHAL_INTLEVEL7_ANDBELOW_MASK 0x003FFFFF
|
||||
|
||||
/* Level of each interrupt: */
|
||||
#define XCHAL_INT0_LEVEL 1
|
||||
#define XCHAL_INT1_LEVEL 1
|
||||
#define XCHAL_INT2_LEVEL 1
|
||||
#define XCHAL_INT3_LEVEL 1
|
||||
#define XCHAL_INT4_LEVEL 1
|
||||
#define XCHAL_INT5_LEVEL 1
|
||||
#define XCHAL_INT6_LEVEL 1
|
||||
#define XCHAL_INT7_LEVEL 1
|
||||
#define XCHAL_INT8_LEVEL 2
|
||||
#define XCHAL_INT9_LEVEL 3
|
||||
#define XCHAL_INT10_LEVEL 3
|
||||
#define XCHAL_INT11_LEVEL 3
|
||||
#define XCHAL_INT12_LEVEL 4
|
||||
#define XCHAL_INT13_LEVEL 5
|
||||
#define XCHAL_INT14_LEVEL 7
|
||||
#define XCHAL_INT15_LEVEL 1
|
||||
#define XCHAL_INT16_LEVEL 1
|
||||
#define XCHAL_INT17_LEVEL 1
|
||||
#define XCHAL_INT18_LEVEL 1
|
||||
#define XCHAL_INT19_LEVEL 1
|
||||
#define XCHAL_INT20_LEVEL 1
|
||||
#define XCHAL_INT21_LEVEL 3
|
||||
#define XCHAL_DEBUGLEVEL 6 /* debug interrupt level */
|
||||
#define XCHAL_HAVE_DEBUG_EXTERN_INT 1 /* OCD external db interrupt */
|
||||
#define XCHAL_NMILEVEL 7 /* NMI "level" (for use with
|
||||
EXCSAVE/EPS/EPC_n, RFI n) */
|
||||
|
||||
/* Type of each interrupt: */
|
||||
#define XCHAL_INT0_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT1_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT3_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT5_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT6_TYPE XTHAL_INTTYPE_TIMER
|
||||
#define XCHAL_INT7_TYPE XTHAL_INTTYPE_SOFTWARE
|
||||
#define XCHAL_INT8_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT9_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT10_TYPE XTHAL_INTTYPE_TIMER
|
||||
#define XCHAL_INT11_TYPE XTHAL_INTTYPE_SOFTWARE
|
||||
#define XCHAL_INT12_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
|
||||
#define XCHAL_INT13_TYPE XTHAL_INTTYPE_TIMER
|
||||
#define XCHAL_INT14_TYPE XTHAL_INTTYPE_NMI
|
||||
#define XCHAL_INT15_TYPE XTHAL_INTTYPE_EXTERN_EDGE
|
||||
#define XCHAL_INT16_TYPE XTHAL_INTTYPE_EXTERN_EDGE
|
||||
#define XCHAL_INT17_TYPE XTHAL_INTTYPE_EXTERN_EDGE
|
||||
#define XCHAL_INT18_TYPE XTHAL_INTTYPE_EXTERN_EDGE
|
||||
#define XCHAL_INT19_TYPE XTHAL_INTTYPE_EXTERN_EDGE
|
||||
#define XCHAL_INT20_TYPE XTHAL_INTTYPE_EXTERN_EDGE
|
||||
#define XCHAL_INT21_TYPE XTHAL_INTTYPE_EXTERN_EDGE
|
||||
|
||||
/* Masks of interrupts for each type of interrupt: */
|
||||
#define XCHAL_INTTYPE_MASK_UNCONFIGURED 0xFFC00000
|
||||
#define XCHAL_INTTYPE_MASK_EXTERN_LEVEL 0x0000133F
|
||||
#define XCHAL_INTTYPE_MASK_EXTERN_EDGE 0x003F8000
|
||||
#define XCHAL_INTTYPE_MASK_NMI 0x00004000
|
||||
#define XCHAL_INTTYPE_MASK_SOFTWARE 0x00000880
|
||||
#define XCHAL_INTTYPE_MASK_TIMER 0x00002440
|
||||
#define XCHAL_INTTYPE_MASK_WRITE_ERROR 0x00000000
|
||||
#define XCHAL_INTTYPE_MASK_DBG_REQUEST 0x00000000
|
||||
#define XCHAL_INTTYPE_MASK_BREAKIN 0x00000000
|
||||
#define XCHAL_INTTYPE_MASK_TRAX 0x00000000
|
||||
#define XCHAL_INTTYPE_MASK_PROFILING 0x00000000
|
||||
#define XCHAL_INTTYPE_MASK_IDMA_DONE 0x00000000
|
||||
#define XCHAL_INTTYPE_MASK_IDMA_ERR 0x00000000
|
||||
#define XCHAL_INTTYPE_MASK_GS_ERR 0x00000000
|
||||
#define XCHAL_INTTYPE_MASK_L2_ERR 0x00000000
|
||||
#define XCHAL_INTTYPE_MASK_L2_STATUS 0x00000000
|
||||
#define XCHAL_INTTYPE_MASK_COR_ECC_ERR 0x00000000
|
||||
|
||||
/* Interrupt numbers assigned to specific interrupt sources: */
|
||||
#define XCHAL_TIMER0_INTERRUPT 6 /* CCOMPARE0 */
|
||||
#define XCHAL_TIMER1_INTERRUPT 10 /* CCOMPARE1 */
|
||||
#define XCHAL_TIMER2_INTERRUPT 13 /* CCOMPARE2 */
|
||||
#define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED
|
||||
#define XCHAL_NMI_INTERRUPT 14 /* non-maskable interrupt */
|
||||
|
||||
/* Interrupt numbers for levels at which only one interrupt is configured: */
|
||||
#define XCHAL_INTLEVEL2_NUM 8
|
||||
#define XCHAL_INTLEVEL4_NUM 12
|
||||
#define XCHAL_INTLEVEL5_NUM 13
|
||||
#define XCHAL_INTLEVEL7_NUM 14
|
||||
/* (There are many interrupts each at level(s) 1, 3.) */
|
||||
|
||||
|
||||
/*
|
||||
* External interrupt mapping.
|
||||
* These macros describe how Xtensa processor interrupt numbers
|
||||
* (as numbered internally, eg. in INTERRUPT and INTENABLE registers)
|
||||
* map to external BInterrupt<n> pins, for those interrupts
|
||||
* configured as external (level-triggered, edge-triggered, or NMI).
|
||||
* See the Xtensa processor databook for more details.
|
||||
*/
|
||||
|
||||
/* Core interrupt numbers mapped to each EXTERNAL BInterrupt pin number: */
|
||||
#define XCHAL_EXTINT0_NUM 0 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT1_NUM 1 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT2_NUM 2 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT3_NUM 3 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT4_NUM 4 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT5_NUM 5 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT6_NUM 8 /* (intlevel 2) */
|
||||
#define XCHAL_EXTINT7_NUM 9 /* (intlevel 3) */
|
||||
#define XCHAL_EXTINT8_NUM 12 /* (intlevel 4) */
|
||||
#define XCHAL_EXTINT9_NUM 14 /* (intlevel 7) */
|
||||
#define XCHAL_EXTINT10_NUM 15 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT11_NUM 16 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT12_NUM 17 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT13_NUM 18 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT14_NUM 19 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT15_NUM 20 /* (intlevel 1) */
|
||||
#define XCHAL_EXTINT16_NUM 21 /* (intlevel 3) */
|
||||
/* EXTERNAL BInterrupt pin numbers mapped to each core interrupt number: */
|
||||
#define XCHAL_INT0_EXTNUM 0 /* (intlevel 1) */
|
||||
#define XCHAL_INT1_EXTNUM 1 /* (intlevel 1) */
|
||||
#define XCHAL_INT2_EXTNUM 2 /* (intlevel 1) */
|
||||
#define XCHAL_INT3_EXTNUM 3 /* (intlevel 1) */
|
||||
#define XCHAL_INT4_EXTNUM 4 /* (intlevel 1) */
|
||||
#define XCHAL_INT5_EXTNUM 5 /* (intlevel 1) */
|
||||
#define XCHAL_INT8_EXTNUM 6 /* (intlevel 2) */
|
||||
#define XCHAL_INT9_EXTNUM 7 /* (intlevel 3) */
|
||||
#define XCHAL_INT12_EXTNUM 8 /* (intlevel 4) */
|
||||
#define XCHAL_INT14_EXTNUM 9 /* (intlevel 7) */
|
||||
#define XCHAL_INT15_EXTNUM 10 /* (intlevel 1) */
|
||||
#define XCHAL_INT16_EXTNUM 11 /* (intlevel 1) */
|
||||
#define XCHAL_INT17_EXTNUM 12 /* (intlevel 1) */
|
||||
#define XCHAL_INT18_EXTNUM 13 /* (intlevel 1) */
|
||||
#define XCHAL_INT19_EXTNUM 14 /* (intlevel 1) */
|
||||
#define XCHAL_INT20_EXTNUM 15 /* (intlevel 1) */
|
||||
#define XCHAL_INT21_EXTNUM 16 /* (intlevel 3) */
|
||||
|
||||
#define XCHAL_HAVE_ISB 0 /* No ISB */
|
||||
#define XCHAL_ISB_VADDR 0 /* N/A */
|
||||
#define XCHAL_HAVE_ITB 0 /* No ITB */
|
||||
#define XCHAL_ITB_VADDR 0 /* N/A */
|
||||
|
||||
#define XCHAL_HAVE_KSL 0 /* Kernel Stack Limit */
|
||||
#define XCHAL_HAVE_ISL 0 /* Interrupt Stack Limit */
|
||||
#define XCHAL_HAVE_PSL 0 /* Pageable Stack Limit */
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
EXCEPTIONS and VECTORS
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
#define XCHAL_XEA_VERSION 2 /* Xtensa Exception Architecture
|
||||
number: 1 == XEA1 (until T1050)
|
||||
2 == XEA2 (T1040 onwards)
|
||||
3 == XEA3 (LX8/NX/SX onwards)
|
||||
0 == XEAX (extern) or TX */
|
||||
#define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */
|
||||
#define XCHAL_HAVE_XEA2 1 /* Exception Architecture 2 */
|
||||
#define XCHAL_HAVE_XEA3 0 /* Exception Architecture 3 */
|
||||
#define XCHAL_HAVE_XEAX 0 /* External Exception Arch. */
|
||||
#define XCHAL_HAVE_EXCEPTIONS 1 /* exception option */
|
||||
#define XCHAL_HAVE_IMPRECISE_EXCEPTIONS 0 /* imprecise exception option */
|
||||
#define XCHAL_EXCCAUSE_NUM 64 /* Number of exceptions */
|
||||
#define XCHAL_HAVE_HALT 0 /* halt architecture option */
|
||||
#define XCHAL_HAVE_BOOTLOADER 0 /* boot loader (for TX) */
|
||||
#define XCHAL_HAVE_MEM_ECC_PARITY 0 /* local memory ECC/parity */
|
||||
#define XCHAL_HAVE_VECTOR_SELECT 1 /* relocatable vectors */
|
||||
#define XCHAL_HAVE_VECBASE 1 /* relocatable vectors */
|
||||
#define XCHAL_VECBASE_RESET_VADDR 0x00002000 /* VECBASE reset value */
|
||||
#define XCHAL_VECBASE_RESET_PADDR 0x00002000
|
||||
#define XCHAL_RESET_VECBASE_OVERLAP 0 /* UNUSED */
|
||||
|
||||
#define XCHAL_RESET_VECTOR0_VADDR 0xFE000000
|
||||
#define XCHAL_RESET_VECTOR0_PADDR 0xFE000000
|
||||
#define XCHAL_RESET_VECTOR1_VADDR 0x00001000
|
||||
#define XCHAL_RESET_VECTOR1_PADDR 0x00001000
|
||||
#define XCHAL_RESET_VECTOR_VADDR XCHAL_RESET_VECTOR0_VADDR
|
||||
#define XCHAL_RESET_VECTOR_PADDR XCHAL_RESET_VECTOR0_PADDR
|
||||
#define XCHAL_USER_VECOFS 0x00000340
|
||||
#define XCHAL_USER_VECTOR_VADDR 0x00002340
|
||||
#define XCHAL_USER_VECTOR_PADDR 0x00002340
|
||||
#define XCHAL_KERNEL_VECOFS 0x00000300
|
||||
#define XCHAL_KERNEL_VECTOR_VADDR 0x00002300
|
||||
#define XCHAL_KERNEL_VECTOR_PADDR 0x00002300
|
||||
#define XCHAL_DOUBLEEXC_VECOFS 0x000003C0
|
||||
#define XCHAL_DOUBLEEXC_VECTOR_VADDR 0x000023C0
|
||||
#define XCHAL_DOUBLEEXC_VECTOR_PADDR 0x000023C0
|
||||
#define XCHAL_WINDOW_OF4_VECOFS 0x00000000
|
||||
#define XCHAL_WINDOW_UF4_VECOFS 0x00000040
|
||||
#define XCHAL_WINDOW_OF8_VECOFS 0x00000080
|
||||
#define XCHAL_WINDOW_UF8_VECOFS 0x000000C0
|
||||
#define XCHAL_WINDOW_OF12_VECOFS 0x00000100
|
||||
#define XCHAL_WINDOW_UF12_VECOFS 0x00000140
|
||||
#define XCHAL_WINDOW_VECTORS_VADDR 0x00002000
|
||||
#define XCHAL_WINDOW_VECTORS_PADDR 0x00002000
|
||||
#define XCHAL_INTLEVEL2_VECOFS 0x00000180
|
||||
#define XCHAL_INTLEVEL2_VECTOR_VADDR 0x00002180
|
||||
#define XCHAL_INTLEVEL2_VECTOR_PADDR 0x00002180
|
||||
#define XCHAL_INTLEVEL3_VECOFS 0x000001C0
|
||||
#define XCHAL_INTLEVEL3_VECTOR_VADDR 0x000021C0
|
||||
#define XCHAL_INTLEVEL3_VECTOR_PADDR 0x000021C0
|
||||
#define XCHAL_INTLEVEL4_VECOFS 0x00000200
|
||||
#define XCHAL_INTLEVEL4_VECTOR_VADDR 0x00002200
|
||||
#define XCHAL_INTLEVEL4_VECTOR_PADDR 0x00002200
|
||||
#define XCHAL_INTLEVEL5_VECOFS 0x00000240
|
||||
#define XCHAL_INTLEVEL5_VECTOR_VADDR 0x00002240
|
||||
#define XCHAL_INTLEVEL5_VECTOR_PADDR 0x00002240
|
||||
#define XCHAL_INTLEVEL6_VECOFS 0x00000280
|
||||
#define XCHAL_INTLEVEL6_VECTOR_VADDR 0x00002280
|
||||
#define XCHAL_INTLEVEL6_VECTOR_PADDR 0x00002280
|
||||
#define XCHAL_DEBUG_VECOFS XCHAL_INTLEVEL6_VECOFS
|
||||
#define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL6_VECTOR_VADDR
|
||||
#define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL6_VECTOR_PADDR
|
||||
#define XCHAL_NMI_VECOFS 0x000002C0
|
||||
#define XCHAL_NMI_VECTOR_VADDR 0x000022C0
|
||||
#define XCHAL_NMI_VECTOR_PADDR 0x000022C0
|
||||
#define XCHAL_INTLEVEL7_VECOFS XCHAL_NMI_VECOFS
|
||||
#define XCHAL_INTLEVEL7_VECTOR_VADDR XCHAL_NMI_VECTOR_VADDR
|
||||
#define XCHAL_INTLEVEL7_VECTOR_PADDR XCHAL_NMI_VECTOR_PADDR
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
DEBUG MODULE
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
/* Misc */
|
||||
#define XCHAL_HAVE_DEBUG_ERI 0 /* ERI to debug module */
|
||||
#define XCHAL_HAVE_DEBUG_APB 0 /* APB to debug module */
|
||||
#define XCHAL_HAVE_DEBUG_JTAG 1 /* JTAG to debug module */
|
||||
|
||||
/* On-Chip Debug (OCD) */
|
||||
#define XCHAL_HAVE_OCD 1 /* OnChipDebug option */
|
||||
#define XCHAL_NUM_IBREAK 2 /* number of IBREAKn regs */
|
||||
#define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */
|
||||
#define XCHAL_HAVE_OCD_DIR_ARRAY 0 /* faster OCD option (to LX4) */
|
||||
#define XCHAL_HAVE_OCD_LS32DDR 1 /* L32DDR/S32DDR (faster OCD) */
|
||||
|
||||
/* TRAX (in core) */
|
||||
#define XCHAL_HAVE_TRAX 0 /* TRAX in debug module */
|
||||
#define XCHAL_TRAX_MEM_SIZE 0 /* TRAX memory size in bytes */
|
||||
#define XCHAL_TRAX_MEM_SHAREABLE 0 /* start/end regs; ready sig. */
|
||||
#define XCHAL_TRAX_ATB_WIDTH 0 /* ATB width (bits), 0=no ATB */
|
||||
#define XCHAL_TRAX_TIME_WIDTH 0 /* timestamp bitwidth, 0=none */
|
||||
|
||||
/* Perf counters */
|
||||
#define XCHAL_NUM_PERF_COUNTERS 0 /* performance counters */
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
MMU
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
/* See core-matmap.h header file for more details. */
|
||||
|
||||
#define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */
|
||||
#define XCHAL_HAVE_SPANNING_WAY 1 /* one way maps I+D 4GB vaddr */
|
||||
#define XCHAL_SPANNING_WAY 6 /* TLB spanning way number */
|
||||
#define XCHAL_HAVE_IDENTITY_MAP 0 /* vaddr == paddr always */
|
||||
#define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */
|
||||
#define XCHAL_HAVE_MIMIC_CACHEATTR 0 /* region protection */
|
||||
#define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */
|
||||
#define XCHAL_HAVE_PTP_MMU 1 /* full MMU (with page table
|
||||
[autorefill] and protection)
|
||||
usable for an MMU-based OS */
|
||||
|
||||
/* If none of the above last 5 are set, it's a custom TLB configuration. */
|
||||
#define XCHAL_ITLB_ARF_ENTRIES_LOG2 2 /* log2(autorefill way size) */
|
||||
#define XCHAL_DTLB_ARF_ENTRIES_LOG2 2 /* log2(autorefill way size) */
|
||||
|
||||
#define XCHAL_MMU_ASID_BITS 8 /* number of bits in ASIDs */
|
||||
#define XCHAL_MMU_RINGS 4 /* number of rings (1..4) */
|
||||
#define XCHAL_MMU_RING_BITS 2 /* num of bits in RING field */
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
MPU
|
||||
----------------------------------------------------------------------*/
|
||||
#define XCHAL_HAVE_MPU 0
|
||||
#define XCHAL_MPU_ENTRIES 0
|
||||
|
||||
#define XCHAL_MPU_ALIGN_REQ 1 /* MPU requires alignment of entries to background map */
|
||||
#define XCHAL_MPU_BACKGROUND_ENTRIES 0 /* number of entries in bg map*/
|
||||
#define XCHAL_MPU_BG_CACHEADRDIS 0 /* default CACHEADRDIS for bg */
|
||||
|
||||
#define XCHAL_MPU_ALIGN_BITS 0
|
||||
#define XCHAL_MPU_ALIGN 0
|
||||
|
||||
#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */
|
||||
|
||||
|
||||
#endif /* XTENSA_CORE_CONFIGURATION_H_ */
|
||||
|
||||
717
target/xtensa/core-de233_fpu/core-matmap.h
Normal file
717
target/xtensa/core-de233_fpu/core-matmap.h
Normal file
@ -0,0 +1,717 @@
|
||||
/*
|
||||
* xtensa/config/core-matmap.h -- Memory access and translation mapping
|
||||
* parameters (CHAL) of the Xtensa processor core configuration.
|
||||
*
|
||||
* If you are using Xtensa Tools, see <xtensa/config/core.h> (which includes
|
||||
* this file) for more details.
|
||||
*
|
||||
* In the Xtensa processor products released to date, all parameters
|
||||
* defined in this file are derivable (at least in theory) from
|
||||
* information contained in the core-isa.h header file.
|
||||
* In particular, the following core configuration parameters are relevant:
|
||||
* XCHAL_HAVE_CACHEATTR
|
||||
* XCHAL_HAVE_MIMIC_CACHEATTR
|
||||
* XCHAL_HAVE_XLT_CACHEATTR
|
||||
* XCHAL_HAVE_PTP_MMU
|
||||
* XCHAL_ITLB_ARF_ENTRIES_LOG2
|
||||
* XCHAL_DTLB_ARF_ENTRIES_LOG2
|
||||
* XCHAL_DCACHE_IS_WRITEBACK
|
||||
* XCHAL_ICACHE_SIZE (presence of I-cache)
|
||||
* XCHAL_DCACHE_SIZE (presence of D-cache)
|
||||
* XCHAL_HW_VERSION_MAJOR
|
||||
* XCHAL_HW_VERSION_MINOR
|
||||
*/
|
||||
|
||||
/* Copyright (c) 1999-2020 Tensilica Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining
|
||||
a copy of this software and associated documentation files (the
|
||||
"Software"), to deal in the Software without restriction, including
|
||||
without limitation the rights to use, copy, modify, merge, publish,
|
||||
distribute, sublicense, and/or sell copies of the Software, and to
|
||||
permit persons to whom the Software is furnished to do so, subject to
|
||||
the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included
|
||||
in all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
|
||||
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
|
||||
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
|
||||
|
||||
|
||||
#ifndef XTENSA_CONFIG_CORE_MATMAP_H
|
||||
#define XTENSA_CONFIG_CORE_MATMAP_H
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
CACHE (MEMORY ACCESS) ATTRIBUTES
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
|
||||
|
||||
/* Cache Attribute encodings -- lists of access modes for each cache attribute: */
|
||||
#define XCHAL_FCA_LIST XTHAL_FAM_EXCEPTION XCHAL_SEP \
|
||||
XTHAL_FAM_BYPASS XCHAL_SEP \
|
||||
XTHAL_FAM_EXCEPTION XCHAL_SEP \
|
||||
XTHAL_FAM_BYPASS XCHAL_SEP \
|
||||
XTHAL_FAM_EXCEPTION XCHAL_SEP \
|
||||
XTHAL_FAM_CACHED XCHAL_SEP \
|
||||
XTHAL_FAM_EXCEPTION XCHAL_SEP \
|
||||
XTHAL_FAM_CACHED XCHAL_SEP \
|
||||
XTHAL_FAM_EXCEPTION XCHAL_SEP \
|
||||
XTHAL_FAM_CACHED XCHAL_SEP \
|
||||
XTHAL_FAM_EXCEPTION XCHAL_SEP \
|
||||
XTHAL_FAM_CACHED XCHAL_SEP \
|
||||
XTHAL_FAM_EXCEPTION XCHAL_SEP \
|
||||
XTHAL_FAM_EXCEPTION XCHAL_SEP \
|
||||
XTHAL_FAM_EXCEPTION XCHAL_SEP \
|
||||
XTHAL_FAM_EXCEPTION
|
||||
#define XCHAL_LCA_LIST XTHAL_LAM_BYPASSG XCHAL_SEP \
|
||||
XTHAL_LAM_BYPASSG XCHAL_SEP \
|
||||
XTHAL_LAM_BYPASSG XCHAL_SEP \
|
||||
XTHAL_LAM_BYPASSG XCHAL_SEP \
|
||||
XTHAL_LAM_CACHED XCHAL_SEP \
|
||||
XTHAL_LAM_CACHED XCHAL_SEP \
|
||||
XTHAL_LAM_CACHED XCHAL_SEP \
|
||||
XTHAL_LAM_CACHED XCHAL_SEP \
|
||||
XTHAL_LAM_CACHED XCHAL_SEP \
|
||||
XTHAL_LAM_CACHED XCHAL_SEP \
|
||||
XTHAL_LAM_CACHED XCHAL_SEP \
|
||||
XTHAL_LAM_CACHED XCHAL_SEP \
|
||||
XTHAL_LAM_EXCEPTION XCHAL_SEP \
|
||||
XTHAL_LAM_EXCEPTION XCHAL_SEP \
|
||||
XTHAL_LAM_EXCEPTION XCHAL_SEP \
|
||||
XTHAL_LAM_EXCEPTION
|
||||
#define XCHAL_SCA_LIST XTHAL_SAM_EXCEPTION XCHAL_SEP \
|
||||
XTHAL_SAM_EXCEPTION XCHAL_SEP \
|
||||
XTHAL_SAM_BYPASS XCHAL_SEP \
|
||||
XTHAL_SAM_BYPASS XCHAL_SEP \
|
||||
XTHAL_SAM_EXCEPTION XCHAL_SEP \
|
||||
XTHAL_SAM_EXCEPTION XCHAL_SEP \
|
||||
XTHAL_SAM_WRITEBACK XCHAL_SEP \
|
||||
XTHAL_SAM_WRITEBACK XCHAL_SEP \
|
||||
XTHAL_SAM_EXCEPTION XCHAL_SEP \
|
||||
XTHAL_SAM_EXCEPTION XCHAL_SEP \
|
||||
XTHAL_SAM_WRITETHRU XCHAL_SEP \
|
||||
XTHAL_SAM_WRITETHRU XCHAL_SEP \
|
||||
XTHAL_SAM_EXCEPTION XCHAL_SEP \
|
||||
XTHAL_SAM_EXCEPTION XCHAL_SEP \
|
||||
XTHAL_SAM_EXCEPTION XCHAL_SEP \
|
||||
XTHAL_SAM_EXCEPTION
|
||||
|
||||
#define XCHAL_CA_R (0xC0 | 0x40000000)
|
||||
#define XCHAL_CA_RX (0xD0 | 0x40000000)
|
||||
#define XCHAL_CA_RW (0xE0 | 0x40000000)
|
||||
#define XCHAL_CA_RWX (0xF0 | 0x40000000)
|
||||
|
||||
/*
|
||||
* Specific encoded cache attribute values of general interest.
|
||||
* If a specific cache mode is not available, the closest available
|
||||
* one is returned instead (eg. writethru instead of writeback,
|
||||
* bypass instead of writethru).
|
||||
*/
|
||||
#define XCHAL_CA_BYPASS 3 /* cache disabled (bypassed) mode */
|
||||
#define XCHAL_CA_WRITETHRU 11 /* cache enabled (write-through) mode */
|
||||
#define XCHAL_CA_WRITEBACK 7 /* cache enabled (write-back) mode */
|
||||
#define XCHAL_HAVE_CA_WRITEBACK_NOALLOC 0 /* write-back no-allocate availability */
|
||||
#define XCHAL_CA_WRITEBACK_NOALLOC 7 /* cache enabled (write-back no-allocate) mode */
|
||||
#define XCHAL_CA_BYPASS_RX 1 /* cache disabled (bypassed) mode (no write) */
|
||||
#define XCHAL_CA_WRITETHRU_RX 9 /* cache enabled (write-through) mode (no write) */
|
||||
#define XCHAL_CA_WRITEBACK_RX 5 /* cache enabled (write-back) mode (no write) */
|
||||
#define XCHAL_CA_WRITEBACK_NOALLOC_RX 5 /* cache enabled (write-back no-allocate) mode (no write) */
|
||||
#define XCHAL_CA_BYPASS_RW 2 /* cache disabled (bypassed) mode (no exec) */
|
||||
#define XCHAL_CA_WRITETHRU_RW 10 /* cache enabled (write-through) mode (no exec) */
|
||||
#define XCHAL_CA_WRITEBACK_RW 6 /* cache enabled (write-back) mode (no exec) */
|
||||
#define XCHAL_CA_WRITEBACK_NOALLOC_RW 6 /* cache enabled (write-back no-allocate) mode (no exec) */
|
||||
#define XCHAL_CA_BYPASS_R 0 /* cache disabled (bypassed) mode (no exec, no write) */
|
||||
#define XCHAL_CA_WRITETHRU_R 8 /* cache enabled (write-through) mode (no exec, no write) */
|
||||
#define XCHAL_CA_WRITEBACK_R 4 /* cache enabled (write-back) mode (no exec, no write) */
|
||||
#define XCHAL_CA_WRITEBACK_NOALLOC_R 4 /* cache enabled (write-back no-allocate) mode (no exec, no write) */
|
||||
#define XCHAL_CA_ILLEGAL 12 /* no access allowed (all cause exceptions) mode */
|
||||
|
||||
/*----------------------------------------------------------------------
|
||||
MMU
|
||||
----------------------------------------------------------------------*/
|
||||
|
||||
/*
|
||||
* General notes on MMU parameters.
|
||||
*
|
||||
* Terminology:
|
||||
* ASID = address-space ID (acts as an "extension" of virtual addresses)
|
||||
* VPN = virtual page number
|
||||
* PPN = physical page number
|
||||
* CA = encoded cache attribute (access modes)
|
||||
* TLB = translation look-aside buffer (term is stretched somewhat here)
|
||||
* I = instruction (fetch accesses)
|
||||
* D = data (load and store accesses)
|
||||
* way = each TLB (ITLB and DTLB) consists of a number of "ways"
|
||||
* that simultaneously match the virtual address of an access;
|
||||
* a TLB successfully translates a virtual address if exactly
|
||||
* one way matches the vaddr; if none match, it is a miss;
|
||||
* if multiple match, one gets a "multihit" exception;
|
||||
* each way can be independently configured in terms of number of
|
||||
* entries, page sizes, which fields are writable or constant, etc.
|
||||
* set = group of contiguous ways with exactly identical parameters
|
||||
* ARF = auto-refill; hardware services a 1st-level miss by loading a PTE
|
||||
* from the page table and storing it in one of the auto-refill ways;
|
||||
* if this PTE load also misses, a miss exception is posted for s/w.
|
||||
* min-wired = a "min-wired" way can be used to map a single (minimum-sized)
|
||||
* page arbitrarily under program control; it has a single entry,
|
||||
* is non-auto-refill (some other way(s) must be auto-refill),
|
||||
* all its fields (VPN, PPN, ASID, CA) are all writable, and it
|
||||
* supports the XCHAL_MMU_MIN_PTE_PAGE_SIZE page size (a current
|
||||
* restriction is that this be the only page size it supports).
|
||||
*
|
||||
* TLB way entries are virtually indexed.
|
||||
* TLB ways that support multiple page sizes:
|
||||
* - must have all writable VPN and PPN fields;
|
||||
* - can only use one page size at any given time (eg. setup at startup),
|
||||
* selected by the respective ITLBCFG or DTLBCFG special register,
|
||||
* whose bits n*4+3 .. n*4 index the list of page sizes for way n
|
||||
* (XCHAL_xTLB_SETm_PAGESZ_LOG2_LIST for set m corresponding to way n);
|
||||
* this list may be sparse for auto-refill ways because auto-refill
|
||||
* ways have independent lists of supported page sizes sharing a
|
||||
* common encoding with PTE entries; the encoding is the index into
|
||||
* this list; unsupported sizes for a given way are zero in the list;
|
||||
* selecting unsupported sizes results in undefine hardware behaviour;
|
||||
* - is only possible for ways 0 thru 7 (due to ITLBCFG/DTLBCFG definition).
|
||||
*/
|
||||
|
||||
#define XCHAL_MMU_ASID_INVALID 0 /* ASID value indicating invalid address space */
|
||||
#define XCHAL_MMU_ASID_KERNEL 1 /* ASID value indicating kernel (ring 0) address space */
|
||||
#define XCHAL_MMU_SR_BITS 0 /* number of size-restriction bits supported */
|
||||
#define XCHAL_MMU_CA_BITS 4 /* number of bits needed to hold cache attribute encoding */
|
||||
#define XCHAL_MMU_MAX_PTE_PAGE_SIZE 12 /* max page size in a PTE structure (log2) */
|
||||
#define XCHAL_MMU_MIN_PTE_PAGE_SIZE 12 /* min page size in a PTE structure (log2) */
|
||||
|
||||
|
||||
/*** Instruction TLB: ***/
|
||||
|
||||
#define XCHAL_ITLB_WAY_BITS 3 /* number of bits holding the ways */
|
||||
#define XCHAL_ITLB_WAYS 7 /* number of ways (n-way set-associative TLB) */
|
||||
#define XCHAL_ITLB_ARF_WAYS 4 /* number of auto-refill ways */
|
||||
#define XCHAL_ITLB_SETS 7 /* number of sets (groups of ways with identical settings) */
|
||||
|
||||
/* Way set to which each way belongs: */
|
||||
#define XCHAL_ITLB_WAY0_SET 0
|
||||
#define XCHAL_ITLB_WAY1_SET 1
|
||||
#define XCHAL_ITLB_WAY2_SET 2
|
||||
#define XCHAL_ITLB_WAY3_SET 3
|
||||
#define XCHAL_ITLB_WAY4_SET 4
|
||||
#define XCHAL_ITLB_WAY5_SET 5
|
||||
#define XCHAL_ITLB_WAY6_SET 6
|
||||
|
||||
/* Ways sets that are used by hardware auto-refill (ARF): */
|
||||
#define XCHAL_ITLB_ARF_SETS 4 /* number of auto-refill sets */
|
||||
#define XCHAL_ITLB_ARF_SET0 0 /* index of n'th auto-refill set */
|
||||
#define XCHAL_ITLB_ARF_SET1 1 /* index of n'th auto-refill set */
|
||||
#define XCHAL_ITLB_ARF_SET2 2 /* index of n'th auto-refill set */
|
||||
#define XCHAL_ITLB_ARF_SET3 3 /* index of n'th auto-refill set */
|
||||
|
||||
/* Way sets that are "min-wired" (see terminology comment above): */
|
||||
#define XCHAL_ITLB_MINWIRED_SETS 0 /* number of "min-wired" sets */
|
||||
|
||||
|
||||
/* ITLB way set 0 (group of ways 0 thru 0): */
|
||||
#define XCHAL_ITLB_SET0_WAY 0 /* index of first way in this way set */
|
||||
#define XCHAL_ITLB_SET0_WAYS 1 /* number of (contiguous) ways in this way set */
|
||||
#define XCHAL_ITLB_SET0_ENTRIES_LOG2 2 /* log2(number of entries in this way) */
|
||||
#define XCHAL_ITLB_SET0_ENTRIES 4 /* number of entries in this way (always a power of 2) */
|
||||
#define XCHAL_ITLB_SET0_ARF 1 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
|
||||
#define XCHAL_ITLB_SET0_PAGESIZES 1 /* number of supported page sizes in this way */
|
||||
#define XCHAL_ITLB_SET0_PAGESZ_BITS 0 /* number of bits to encode the page size */
|
||||
#define XCHAL_ITLB_SET0_PAGESZ_LOG2_MIN 12 /* log2(minimum supported page size) */
|
||||
#define XCHAL_ITLB_SET0_PAGESZ_LOG2_MAX 12 /* log2(maximum supported page size) */
|
||||
#define XCHAL_ITLB_SET0_PAGESZ_LOG2_LIST 12 /* list of log2(page size)s, separated by XCHAL_SEP;
|
||||
2^PAGESZ_BITS entries in list, unsupported entries are zero */
|
||||
#define XCHAL_ITLB_SET0_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */
|
||||
#define XCHAL_ITLB_SET0_VPN_CONSTMASK 0 /* constant VPN bits, not including entry index bits; 0 if all writable */
|
||||
#define XCHAL_ITLB_SET0_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */
|
||||
#define XCHAL_ITLB_SET0_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */
|
||||
#define XCHAL_ITLB_SET0_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */
|
||||
#define XCHAL_ITLB_SET0_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */
|
||||
#define XCHAL_ITLB_SET0_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */
|
||||
#define XCHAL_ITLB_SET0_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */
|
||||
|
||||
/* ITLB way set 1 (group of ways 1 thru 1): */
|
||||
#define XCHAL_ITLB_SET1_WAY 1 /* index of first way in this way set */
|
||||
#define XCHAL_ITLB_SET1_WAYS 1 /* number of (contiguous) ways in this way set */
|
||||
#define XCHAL_ITLB_SET1_ENTRIES_LOG2 2 /* log2(number of entries in this way) */
|
||||
#define XCHAL_ITLB_SET1_ENTRIES 4 /* number of entries in this way (always a power of 2) */
|
||||
#define XCHAL_ITLB_SET1_ARF 1 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
|
||||
#define XCHAL_ITLB_SET1_PAGESIZES 1 /* number of supported page sizes in this way */
|
||||
#define XCHAL_ITLB_SET1_PAGESZ_BITS 0 /* number of bits to encode the page size */
|
||||
#define XCHAL_ITLB_SET1_PAGESZ_LOG2_MIN 12 /* log2(minimum supported page size) */
|
||||
#define XCHAL_ITLB_SET1_PAGESZ_LOG2_MAX 12 /* log2(maximum supported page size) */
|
||||
#define XCHAL_ITLB_SET1_PAGESZ_LOG2_LIST 12 /* list of log2(page size)s, separated by XCHAL_SEP;
|
||||
2^PAGESZ_BITS entries in list, unsupported entries are zero */
|
||||
#define XCHAL_ITLB_SET1_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */
|
||||
#define XCHAL_ITLB_SET1_VPN_CONSTMASK 0 /* constant VPN bits, not including entry index bits; 0 if all writable */
|
||||
#define XCHAL_ITLB_SET1_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */
|
||||
#define XCHAL_ITLB_SET1_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */
|
||||
#define XCHAL_ITLB_SET1_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */
|
||||
#define XCHAL_ITLB_SET1_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */
|
||||
#define XCHAL_ITLB_SET1_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */
|
||||
#define XCHAL_ITLB_SET1_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */
|
||||
|
||||
/* ITLB way set 2 (group of ways 2 thru 2): */
|
||||
#define XCHAL_ITLB_SET2_WAY 2 /* index of first way in this way set */
|
||||
#define XCHAL_ITLB_SET2_WAYS 1 /* number of (contiguous) ways in this way set */
|
||||
#define XCHAL_ITLB_SET2_ENTRIES_LOG2 2 /* log2(number of entries in this way) */
|
||||
#define XCHAL_ITLB_SET2_ENTRIES 4 /* number of entries in this way (always a power of 2) */
|
||||
#define XCHAL_ITLB_SET2_ARF 1 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
|
||||
#define XCHAL_ITLB_SET2_PAGESIZES 1 /* number of supported page sizes in this way */
|
||||
#define XCHAL_ITLB_SET2_PAGESZ_BITS 0 /* number of bits to encode the page size */
|
||||
#define XCHAL_ITLB_SET2_PAGESZ_LOG2_MIN 12 /* log2(minimum supported page size) */
|
||||
#define XCHAL_ITLB_SET2_PAGESZ_LOG2_MAX 12 /* log2(maximum supported page size) */
|
||||
#define XCHAL_ITLB_SET2_PAGESZ_LOG2_LIST 12 /* list of log2(page size)s, separated by XCHAL_SEP;
|
||||
2^PAGESZ_BITS entries in list, unsupported entries are zero */
|
||||
#define XCHAL_ITLB_SET2_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */
|
||||
#define XCHAL_ITLB_SET2_VPN_CONSTMASK 0 /* constant VPN bits, not including entry index bits; 0 if all writable */
|
||||
#define XCHAL_ITLB_SET2_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */
|
||||
#define XCHAL_ITLB_SET2_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */
|
||||
#define XCHAL_ITLB_SET2_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */
|
||||
#define XCHAL_ITLB_SET2_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */
|
||||
#define XCHAL_ITLB_SET2_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */
|
||||
#define XCHAL_ITLB_SET2_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */
|
||||
|
||||
/* ITLB way set 3 (group of ways 3 thru 3): */
|
||||
#define XCHAL_ITLB_SET3_WAY 3 /* index of first way in this way set */
|
||||
#define XCHAL_ITLB_SET3_WAYS 1 /* number of (contiguous) ways in this way set */
|
||||
#define XCHAL_ITLB_SET3_ENTRIES_LOG2 2 /* log2(number of entries in this way) */
|
||||
#define XCHAL_ITLB_SET3_ENTRIES 4 /* number of entries in this way (always a power of 2) */
|
||||
#define XCHAL_ITLB_SET3_ARF 1 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
|
||||
#define XCHAL_ITLB_SET3_PAGESIZES 1 /* number of supported page sizes in this way */
|
||||
#define XCHAL_ITLB_SET3_PAGESZ_BITS 0 /* number of bits to encode the page size */
|
||||
#define XCHAL_ITLB_SET3_PAGESZ_LOG2_MIN 12 /* log2(minimum supported page size) */
|
||||
#define XCHAL_ITLB_SET3_PAGESZ_LOG2_MAX 12 /* log2(maximum supported page size) */
|
||||
#define XCHAL_ITLB_SET3_PAGESZ_LOG2_LIST 12 /* list of log2(page size)s, separated by XCHAL_SEP;
|
||||
2^PAGESZ_BITS entries in list, unsupported entries are zero */
|
||||
#define XCHAL_ITLB_SET3_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */
|
||||
#define XCHAL_ITLB_SET3_VPN_CONSTMASK 0 /* constant VPN bits, not including entry index bits; 0 if all writable */
|
||||
#define XCHAL_ITLB_SET3_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */
|
||||
#define XCHAL_ITLB_SET3_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */
|
||||
#define XCHAL_ITLB_SET3_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */
|
||||
#define XCHAL_ITLB_SET3_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */
|
||||
#define XCHAL_ITLB_SET3_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */
|
||||
#define XCHAL_ITLB_SET3_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */
|
||||
|
||||
/* ITLB way set 4 (group of ways 4 thru 4): */
|
||||
#define XCHAL_ITLB_SET4_WAY 4 /* index of first way in this way set */
|
||||
#define XCHAL_ITLB_SET4_WAYS 1 /* number of (contiguous) ways in this way set */
|
||||
#define XCHAL_ITLB_SET4_ENTRIES_LOG2 2 /* log2(number of entries in this way) */
|
||||
#define XCHAL_ITLB_SET4_ENTRIES 4 /* number of entries in this way (always a power of 2) */
|
||||
#define XCHAL_ITLB_SET4_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
|
||||
#define XCHAL_ITLB_SET4_PAGESIZES 4 /* number of supported page sizes in this way */
|
||||
#define XCHAL_ITLB_SET4_PAGESZ_BITS 2 /* number of bits to encode the page size */
|
||||
#define XCHAL_ITLB_SET4_PAGESZ_LOG2_MIN 20 /* log2(minimum supported page size) */
|
||||
#define XCHAL_ITLB_SET4_PAGESZ_LOG2_MAX 26 /* log2(maximum supported page size) */
|
||||
#define XCHAL_ITLB_SET4_PAGESZ_LOG2_LIST 20 XCHAL_SEP 22 XCHAL_SEP 24 XCHAL_SEP 26 /* list of log2(page size)s, separated by XCHAL_SEP;
|
||||
2^PAGESZ_BITS entries in list, unsupported entries are zero */
|
||||
#define XCHAL_ITLB_SET4_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */
|
||||
#define XCHAL_ITLB_SET4_VPN_CONSTMASK 0 /* constant VPN bits, not including entry index bits; 0 if all writable */
|
||||
#define XCHAL_ITLB_SET4_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */
|
||||
#define XCHAL_ITLB_SET4_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */
|
||||
#define XCHAL_ITLB_SET4_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */
|
||||
#define XCHAL_ITLB_SET4_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */
|
||||
#define XCHAL_ITLB_SET4_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */
|
||||
#define XCHAL_ITLB_SET4_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */
|
||||
|
||||
/* ITLB way set 5 (group of ways 5 thru 5): */
|
||||
#define XCHAL_ITLB_SET5_WAY 5 /* index of first way in this way set */
|
||||
#define XCHAL_ITLB_SET5_WAYS 1 /* number of (contiguous) ways in this way set */
|
||||
#define XCHAL_ITLB_SET5_ENTRIES_LOG2 2 /* log2(number of entries in this way) */
|
||||
#define XCHAL_ITLB_SET5_ENTRIES 4 /* number of entries in this way (always a power of 2) */
|
||||
#define XCHAL_ITLB_SET5_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
|
||||
#define XCHAL_ITLB_SET5_PAGESIZES 2 /* number of supported page sizes in this way */
|
||||
#define XCHAL_ITLB_SET5_PAGESZ_BITS 1 /* number of bits to encode the page size */
|
||||
#define XCHAL_ITLB_SET5_PAGESZ_LOG2_MIN 27 /* log2(minimum supported page size) */
|
||||
#define XCHAL_ITLB_SET5_PAGESZ_LOG2_MAX 28 /* log2(maximum supported page size) */
|
||||
#define XCHAL_ITLB_SET5_PAGESZ_LOG2_LIST 27 XCHAL_SEP 28 /* list of log2(page size)s, separated by XCHAL_SEP;
|
||||
2^PAGESZ_BITS entries in list, unsupported entries are zero */
|
||||
#define XCHAL_ITLB_SET5_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */
|
||||
#define XCHAL_ITLB_SET5_VPN_CONSTMASK 0 /* constant VPN bits, not including entry index bits; 0 if all writable */
|
||||
#define XCHAL_ITLB_SET5_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */
|
||||
#define XCHAL_ITLB_SET5_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */
|
||||
#define XCHAL_ITLB_SET5_ASID_RESET 1 /* 1 if ASID reset values defined (and all writable); 0 otherwise */
|
||||
#define XCHAL_ITLB_SET5_VPN_RESET 1 /* 1 if VPN reset values defined (and all writable); 0 otherwise */
|
||||
#define XCHAL_ITLB_SET5_PPN_RESET 1 /* 1 if PPN reset values defined (and all writable); 0 otherwise */
|
||||
#define XCHAL_ITLB_SET5_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */
|
||||
/* Reset ASID values for each entry of ITLB way set 5 (because SET5_ASID_RESET is non-zero): */
|
||||
#define XCHAL_ITLB_SET5_E0_ASID_RESET 0x00
|
||||
#define XCHAL_ITLB_SET5_E1_ASID_RESET 0x00
|
||||
#define XCHAL_ITLB_SET5_E2_ASID_RESET 0x00
|
||||
#define XCHAL_ITLB_SET5_E3_ASID_RESET 0x00
|
||||
/* Reset VPN values for each entry of ITLB way set 5 (because SET5_VPN_RESET is non-zero): */
|
||||
#define XCHAL_ITLB_SET5_E0_VPN_RESET 0x00000000
|
||||
#define XCHAL_ITLB_SET5_E1_VPN_RESET 0x00000000
|
||||
#define XCHAL_ITLB_SET5_E2_VPN_RESET 0x00000000
|
||||
#define XCHAL_ITLB_SET5_E3_VPN_RESET 0x00000000
|
||||
/* Reset PPN values for each entry of ITLB way set 5 (because SET5_PPN_RESET is non-zero): */
|
||||
#define XCHAL_ITLB_SET5_E0_PPN_RESET 0x00000000
|
||||
#define XCHAL_ITLB_SET5_E1_PPN_RESET 0x00000000
|
||||
#define XCHAL_ITLB_SET5_E2_PPN_RESET 0x00000000
|
||||
#define XCHAL_ITLB_SET5_E3_PPN_RESET 0x00000000
|
||||
|
||||
/* ITLB way set 6 (group of ways 6 thru 6): */
|
||||
#define XCHAL_ITLB_SET6_WAY 6 /* index of first way in this way set */
|
||||
#define XCHAL_ITLB_SET6_WAYS 1 /* number of (contiguous) ways in this way set */
|
||||
#define XCHAL_ITLB_SET6_ENTRIES_LOG2 3 /* log2(number of entries in this way) */
|
||||
#define XCHAL_ITLB_SET6_ENTRIES 8 /* number of entries in this way (always a power of 2) */
|
||||
#define XCHAL_ITLB_SET6_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
|
||||
#define XCHAL_ITLB_SET6_PAGESIZES 2 /* number of supported page sizes in this way */
|
||||
#define XCHAL_ITLB_SET6_PAGESZ_BITS 1 /* number of bits to encode the page size */
|
||||
#define XCHAL_ITLB_SET6_PAGESZ_LOG2_MIN 28 /* log2(minimum supported page size) */
|
||||
#define XCHAL_ITLB_SET6_PAGESZ_LOG2_MAX 29 /* log2(maximum supported page size) */
|
||||
#define XCHAL_ITLB_SET6_PAGESZ_LOG2_LIST 29 XCHAL_SEP 28 /* list of log2(page size)s, separated by XCHAL_SEP;
|
||||
2^PAGESZ_BITS entries in list, unsupported entries are zero */
|
||||
#define XCHAL_ITLB_SET6_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */
|
||||
#define XCHAL_ITLB_SET6_VPN_CONSTMASK 0 /* constant VPN bits, not including entry index bits; 0 if all writable */
|
||||
#define XCHAL_ITLB_SET6_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */
|
||||
#define XCHAL_ITLB_SET6_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */
|
||||
#define XCHAL_ITLB_SET6_ASID_RESET 1 /* 1 if ASID reset values defined (and all writable); 0 otherwise */
|
||||
#define XCHAL_ITLB_SET6_VPN_RESET 1 /* 1 if VPN reset values defined (and all writable); 0 otherwise */
|
||||
#define XCHAL_ITLB_SET6_PPN_RESET 1 /* 1 if PPN reset values defined (and all writable); 0 otherwise */
|
||||
#define XCHAL_ITLB_SET6_CA_RESET 1 /* 1 if CA reset values defined (and all writable); 0 otherwise */
|
||||
/* Reset ASID values for each entry of ITLB way set 6 (because SET6_ASID_RESET is non-zero): */
|
||||
#define XCHAL_ITLB_SET6_E0_ASID_RESET 0x01
|
||||
#define XCHAL_ITLB_SET6_E1_ASID_RESET 0x01
|
||||
#define XCHAL_ITLB_SET6_E2_ASID_RESET 0x01
|
||||
#define XCHAL_ITLB_SET6_E3_ASID_RESET 0x01
|
||||
#define XCHAL_ITLB_SET6_E4_ASID_RESET 0x01
|
||||
#define XCHAL_ITLB_SET6_E5_ASID_RESET 0x01
|
||||
#define XCHAL_ITLB_SET6_E6_ASID_RESET 0x01
|
||||
#define XCHAL_ITLB_SET6_E7_ASID_RESET 0x01
|
||||
/* Reset VPN values for each entry of ITLB way set 6 (because SET6_VPN_RESET is non-zero): */
|
||||
#define XCHAL_ITLB_SET6_E0_VPN_RESET 0x00000000
|
||||
#define XCHAL_ITLB_SET6_E1_VPN_RESET 0x20000000
|
||||
#define XCHAL_ITLB_SET6_E2_VPN_RESET 0x40000000
|
||||
#define XCHAL_ITLB_SET6_E3_VPN_RESET 0x60000000
|
||||
#define XCHAL_ITLB_SET6_E4_VPN_RESET 0x80000000
|
||||
#define XCHAL_ITLB_SET6_E5_VPN_RESET 0xA0000000
|
||||
#define XCHAL_ITLB_SET6_E6_VPN_RESET 0xC0000000
|
||||
#define XCHAL_ITLB_SET6_E7_VPN_RESET 0xE0000000
|
||||
/* Reset PPN values for each entry of ITLB way set 6 (because SET6_PPN_RESET is non-zero): */
|
||||
#define XCHAL_ITLB_SET6_E0_PPN_RESET 0x00000000
|
||||
#define XCHAL_ITLB_SET6_E1_PPN_RESET 0x20000000
|
||||
#define XCHAL_ITLB_SET6_E2_PPN_RESET 0x40000000
|
||||
#define XCHAL_ITLB_SET6_E3_PPN_RESET 0x60000000
|
||||
#define XCHAL_ITLB_SET6_E4_PPN_RESET 0x80000000
|
||||
#define XCHAL_ITLB_SET6_E5_PPN_RESET 0xA0000000
|
||||
#define XCHAL_ITLB_SET6_E6_PPN_RESET 0xC0000000
|
||||
#define XCHAL_ITLB_SET6_E7_PPN_RESET 0xE0000000
|
||||
/* Reset CA values for each entry of ITLB way set 6 (because SET6_CA_RESET is non-zero): */
|
||||
#define XCHAL_ITLB_SET6_E0_CA_RESET 0x03
|
||||
#define XCHAL_ITLB_SET6_E1_CA_RESET 0x03
|
||||
#define XCHAL_ITLB_SET6_E2_CA_RESET 0x03
|
||||
#define XCHAL_ITLB_SET6_E3_CA_RESET 0x03
|
||||
#define XCHAL_ITLB_SET6_E4_CA_RESET 0x03
|
||||
#define XCHAL_ITLB_SET6_E5_CA_RESET 0x03
|
||||
#define XCHAL_ITLB_SET6_E6_CA_RESET 0x03
|
||||
#define XCHAL_ITLB_SET6_E7_CA_RESET 0x03
|
||||
|
||||
|
||||
/*** Data TLB: ***/
|
||||
|
||||
#define XCHAL_DTLB_WAY_BITS 4 /* number of bits holding the ways */
|
||||
#define XCHAL_DTLB_WAYS 10 /* number of ways (n-way set-associative TLB) */
|
||||
#define XCHAL_DTLB_ARF_WAYS 4 /* number of auto-refill ways */
|
||||
#define XCHAL_DTLB_SETS 10 /* number of sets (groups of ways with identical settings) */
|
||||
|
||||
/* Way set to which each way belongs: */
|
||||
#define XCHAL_DTLB_WAY0_SET 0
|
||||
#define XCHAL_DTLB_WAY1_SET 1
|
||||
#define XCHAL_DTLB_WAY2_SET 2
|
||||
#define XCHAL_DTLB_WAY3_SET 3
|
||||
#define XCHAL_DTLB_WAY4_SET 4
|
||||
#define XCHAL_DTLB_WAY5_SET 5
|
||||
#define XCHAL_DTLB_WAY6_SET 6
|
||||
#define XCHAL_DTLB_WAY7_SET 7
|
||||
#define XCHAL_DTLB_WAY8_SET 8
|
||||
#define XCHAL_DTLB_WAY9_SET 9
|
||||
|
||||
/* Ways sets that are used by hardware auto-refill (ARF): */
|
||||
#define XCHAL_DTLB_ARF_SETS 4 /* number of auto-refill sets */
|
||||
#define XCHAL_DTLB_ARF_SET0 0 /* index of n'th auto-refill set */
|
||||
#define XCHAL_DTLB_ARF_SET1 1 /* index of n'th auto-refill set */
|
||||
#define XCHAL_DTLB_ARF_SET2 2 /* index of n'th auto-refill set */
|
||||
#define XCHAL_DTLB_ARF_SET3 3 /* index of n'th auto-refill set */
|
||||
|
||||
/* Way sets that are "min-wired" (see terminology comment above): */
|
||||
#define XCHAL_DTLB_MINWIRED_SETS 3 /* number of "min-wired" sets */
|
||||
#define XCHAL_DTLB_MINWIRED_SET0 7 /* index of n'th "min-wired" set */
|
||||
#define XCHAL_DTLB_MINWIRED_SET1 8 /* index of n'th "min-wired" set */
|
||||
#define XCHAL_DTLB_MINWIRED_SET2 9 /* index of n'th "min-wired" set */
|
||||
|
||||
|
||||
/* DTLB way set 0 (group of ways 0 thru 0): */
|
||||
#define XCHAL_DTLB_SET0_WAY 0 /* index of first way in this way set */
|
||||
#define XCHAL_DTLB_SET0_WAYS 1 /* number of (contiguous) ways in this way set */
|
||||
#define XCHAL_DTLB_SET0_ENTRIES_LOG2 2 /* log2(number of entries in this way) */
|
||||
#define XCHAL_DTLB_SET0_ENTRIES 4 /* number of entries in this way (always a power of 2) */
|
||||
#define XCHAL_DTLB_SET0_ARF 1 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
|
||||
#define XCHAL_DTLB_SET0_PAGESIZES 1 /* number of supported page sizes in this way */
|
||||
#define XCHAL_DTLB_SET0_PAGESZ_BITS 0 /* number of bits to encode the page size */
|
||||
#define XCHAL_DTLB_SET0_PAGESZ_LOG2_MIN 12 /* log2(minimum supported page size) */
|
||||
#define XCHAL_DTLB_SET0_PAGESZ_LOG2_MAX 12 /* log2(maximum supported page size) */
|
||||
#define XCHAL_DTLB_SET0_PAGESZ_LOG2_LIST 12 /* list of log2(page size)s, separated by XCHAL_SEP;
|
||||
2^PAGESZ_BITS entries in list, unsupported entries are zero */
|
||||
#define XCHAL_DTLB_SET0_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */
|
||||
#define XCHAL_DTLB_SET0_VPN_CONSTMASK 0 /* constant VPN bits, not including entry index bits; 0 if all writable */
|
||||
#define XCHAL_DTLB_SET0_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */
|
||||
#define XCHAL_DTLB_SET0_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */
|
||||
#define XCHAL_DTLB_SET0_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */
|
||||
#define XCHAL_DTLB_SET0_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */
|
||||
#define XCHAL_DTLB_SET0_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */
|
||||
#define XCHAL_DTLB_SET0_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */
|
||||
|
||||
/* DTLB way set 1 (group of ways 1 thru 1): */
|
||||
#define XCHAL_DTLB_SET1_WAY 1 /* index of first way in this way set */
|
||||
#define XCHAL_DTLB_SET1_WAYS 1 /* number of (contiguous) ways in this way set */
|
||||
#define XCHAL_DTLB_SET1_ENTRIES_LOG2 2 /* log2(number of entries in this way) */
|
||||
#define XCHAL_DTLB_SET1_ENTRIES 4 /* number of entries in this way (always a power of 2) */
|
||||
#define XCHAL_DTLB_SET1_ARF 1 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
|
||||
#define XCHAL_DTLB_SET1_PAGESIZES 1 /* number of supported page sizes in this way */
|
||||
#define XCHAL_DTLB_SET1_PAGESZ_BITS 0 /* number of bits to encode the page size */
|
||||
#define XCHAL_DTLB_SET1_PAGESZ_LOG2_MIN 12 /* log2(minimum supported page size) */
|
||||
#define XCHAL_DTLB_SET1_PAGESZ_LOG2_MAX 12 /* log2(maximum supported page size) */
|
||||
#define XCHAL_DTLB_SET1_PAGESZ_LOG2_LIST 12 /* list of log2(page size)s, separated by XCHAL_SEP;
|
||||
2^PAGESZ_BITS entries in list, unsupported entries are zero */
|
||||
#define XCHAL_DTLB_SET1_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */
|
||||
#define XCHAL_DTLB_SET1_VPN_CONSTMASK 0 /* constant VPN bits, not including entry index bits; 0 if all writable */
|
||||
#define XCHAL_DTLB_SET1_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */
|
||||
#define XCHAL_DTLB_SET1_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */
|
||||
#define XCHAL_DTLB_SET1_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */
|
||||
#define XCHAL_DTLB_SET1_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */
|
||||
#define XCHAL_DTLB_SET1_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */
|
||||
#define XCHAL_DTLB_SET1_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */
|
||||
|
||||
/* DTLB way set 2 (group of ways 2 thru 2): */
|
||||
#define XCHAL_DTLB_SET2_WAY 2 /* index of first way in this way set */
|
||||
#define XCHAL_DTLB_SET2_WAYS 1 /* number of (contiguous) ways in this way set */
|
||||
#define XCHAL_DTLB_SET2_ENTRIES_LOG2 2 /* log2(number of entries in this way) */
|
||||
#define XCHAL_DTLB_SET2_ENTRIES 4 /* number of entries in this way (always a power of 2) */
|
||||
#define XCHAL_DTLB_SET2_ARF 1 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
|
||||
#define XCHAL_DTLB_SET2_PAGESIZES 1 /* number of supported page sizes in this way */
|
||||
#define XCHAL_DTLB_SET2_PAGESZ_BITS 0 /* number of bits to encode the page size */
|
||||
#define XCHAL_DTLB_SET2_PAGESZ_LOG2_MIN 12 /* log2(minimum supported page size) */
|
||||
#define XCHAL_DTLB_SET2_PAGESZ_LOG2_MAX 12 /* log2(maximum supported page size) */
|
||||
#define XCHAL_DTLB_SET2_PAGESZ_LOG2_LIST 12 /* list of log2(page size)s, separated by XCHAL_SEP;
|
||||
2^PAGESZ_BITS entries in list, unsupported entries are zero */
|
||||
#define XCHAL_DTLB_SET2_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */
|
||||
#define XCHAL_DTLB_SET2_VPN_CONSTMASK 0 /* constant VPN bits, not including entry index bits; 0 if all writable */
|
||||
#define XCHAL_DTLB_SET2_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */
|
||||
#define XCHAL_DTLB_SET2_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */
|
||||
#define XCHAL_DTLB_SET2_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */
|
||||
#define XCHAL_DTLB_SET2_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */
|
||||
#define XCHAL_DTLB_SET2_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */
|
||||
#define XCHAL_DTLB_SET2_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */
|
||||
|
||||
/* DTLB way set 3 (group of ways 3 thru 3): */
|
||||
#define XCHAL_DTLB_SET3_WAY 3 /* index of first way in this way set */
|
||||
#define XCHAL_DTLB_SET3_WAYS 1 /* number of (contiguous) ways in this way set */
|
||||
#define XCHAL_DTLB_SET3_ENTRIES_LOG2 2 /* log2(number of entries in this way) */
|
||||
#define XCHAL_DTLB_SET3_ENTRIES 4 /* number of entries in this way (always a power of 2) */
|
||||
#define XCHAL_DTLB_SET3_ARF 1 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
|
||||
#define XCHAL_DTLB_SET3_PAGESIZES 1 /* number of supported page sizes in this way */
|
||||
#define XCHAL_DTLB_SET3_PAGESZ_BITS 0 /* number of bits to encode the page size */
|
||||
#define XCHAL_DTLB_SET3_PAGESZ_LOG2_MIN 12 /* log2(minimum supported page size) */
|
||||
#define XCHAL_DTLB_SET3_PAGESZ_LOG2_MAX 12 /* log2(maximum supported page size) */
|
||||
#define XCHAL_DTLB_SET3_PAGESZ_LOG2_LIST 12 /* list of log2(page size)s, separated by XCHAL_SEP;
|
||||
2^PAGESZ_BITS entries in list, unsupported entries are zero */
|
||||
#define XCHAL_DTLB_SET3_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */
|
||||
#define XCHAL_DTLB_SET3_VPN_CONSTMASK 0 /* constant VPN bits, not including entry index bits; 0 if all writable */
|
||||
#define XCHAL_DTLB_SET3_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */
|
||||
#define XCHAL_DTLB_SET3_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */
|
||||
#define XCHAL_DTLB_SET3_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */
|
||||
#define XCHAL_DTLB_SET3_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */
|
||||
#define XCHAL_DTLB_SET3_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */
|
||||
#define XCHAL_DTLB_SET3_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */
|
||||
|
||||
/* DTLB way set 4 (group of ways 4 thru 4): */
|
||||
#define XCHAL_DTLB_SET4_WAY 4 /* index of first way in this way set */
|
||||
#define XCHAL_DTLB_SET4_WAYS 1 /* number of (contiguous) ways in this way set */
|
||||
#define XCHAL_DTLB_SET4_ENTRIES_LOG2 2 /* log2(number of entries in this way) */
|
||||
#define XCHAL_DTLB_SET4_ENTRIES 4 /* number of entries in this way (always a power of 2) */
|
||||
#define XCHAL_DTLB_SET4_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
|
||||
#define XCHAL_DTLB_SET4_PAGESIZES 4 /* number of supported page sizes in this way */
|
||||
#define XCHAL_DTLB_SET4_PAGESZ_BITS 2 /* number of bits to encode the page size */
|
||||
#define XCHAL_DTLB_SET4_PAGESZ_LOG2_MIN 20 /* log2(minimum supported page size) */
|
||||
#define XCHAL_DTLB_SET4_PAGESZ_LOG2_MAX 26 /* log2(maximum supported page size) */
|
||||
#define XCHAL_DTLB_SET4_PAGESZ_LOG2_LIST 20 XCHAL_SEP 22 XCHAL_SEP 24 XCHAL_SEP 26 /* list of log2(page size)s, separated by XCHAL_SEP;
|
||||
2^PAGESZ_BITS entries in list, unsupported entries are zero */
|
||||
#define XCHAL_DTLB_SET4_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */
|
||||
#define XCHAL_DTLB_SET4_VPN_CONSTMASK 0 /* constant VPN bits, not including entry index bits; 0 if all writable */
|
||||
#define XCHAL_DTLB_SET4_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */
|
||||
#define XCHAL_DTLB_SET4_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */
|
||||
#define XCHAL_DTLB_SET4_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */
|
||||
#define XCHAL_DTLB_SET4_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */
|
||||
#define XCHAL_DTLB_SET4_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */
|
||||
#define XCHAL_DTLB_SET4_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */
|
||||
|
||||
/* DTLB way set 5 (group of ways 5 thru 5): */
|
||||
#define XCHAL_DTLB_SET5_WAY 5 /* index of first way in this way set */
|
||||
#define XCHAL_DTLB_SET5_WAYS 1 /* number of (contiguous) ways in this way set */
|
||||
#define XCHAL_DTLB_SET5_ENTRIES_LOG2 2 /* log2(number of entries in this way) */
|
||||
#define XCHAL_DTLB_SET5_ENTRIES 4 /* number of entries in this way (always a power of 2) */
|
||||
#define XCHAL_DTLB_SET5_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
|
||||
#define XCHAL_DTLB_SET5_PAGESIZES 2 /* number of supported page sizes in this way */
|
||||
#define XCHAL_DTLB_SET5_PAGESZ_BITS 1 /* number of bits to encode the page size */
|
||||
#define XCHAL_DTLB_SET5_PAGESZ_LOG2_MIN 27 /* log2(minimum supported page size) */
|
||||
#define XCHAL_DTLB_SET5_PAGESZ_LOG2_MAX 28 /* log2(maximum supported page size) */
|
||||
#define XCHAL_DTLB_SET5_PAGESZ_LOG2_LIST 27 XCHAL_SEP 28 /* list of log2(page size)s, separated by XCHAL_SEP;
|
||||
2^PAGESZ_BITS entries in list, unsupported entries are zero */
|
||||
#define XCHAL_DTLB_SET5_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */
|
||||
#define XCHAL_DTLB_SET5_VPN_CONSTMASK 0 /* constant VPN bits, not including entry index bits; 0 if all writable */
|
||||
#define XCHAL_DTLB_SET5_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */
|
||||
#define XCHAL_DTLB_SET5_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */
|
||||
#define XCHAL_DTLB_SET5_ASID_RESET 1 /* 1 if ASID reset values defined (and all writable); 0 otherwise */
|
||||
#define XCHAL_DTLB_SET5_VPN_RESET 1 /* 1 if VPN reset values defined (and all writable); 0 otherwise */
|
||||
#define XCHAL_DTLB_SET5_PPN_RESET 1 /* 1 if PPN reset values defined (and all writable); 0 otherwise */
|
||||
#define XCHAL_DTLB_SET5_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */
|
||||
/* Reset ASID values for each entry of DTLB way set 5 (because SET5_ASID_RESET is non-zero): */
|
||||
#define XCHAL_DTLB_SET5_E0_ASID_RESET 0x00
|
||||
#define XCHAL_DTLB_SET5_E1_ASID_RESET 0x00
|
||||
#define XCHAL_DTLB_SET5_E2_ASID_RESET 0x00
|
||||
#define XCHAL_DTLB_SET5_E3_ASID_RESET 0x00
|
||||
/* Reset VPN values for each entry of DTLB way set 5 (because SET5_VPN_RESET is non-zero): */
|
||||
#define XCHAL_DTLB_SET5_E0_VPN_RESET 0x00000000
|
||||
#define XCHAL_DTLB_SET5_E1_VPN_RESET 0x00000000
|
||||
#define XCHAL_DTLB_SET5_E2_VPN_RESET 0x00000000
|
||||
#define XCHAL_DTLB_SET5_E3_VPN_RESET 0x00000000
|
||||
/* Reset PPN values for each entry of DTLB way set 5 (because SET5_PPN_RESET is non-zero): */
|
||||
#define XCHAL_DTLB_SET5_E0_PPN_RESET 0x00000000
|
||||
#define XCHAL_DTLB_SET5_E1_PPN_RESET 0x00000000
|
||||
#define XCHAL_DTLB_SET5_E2_PPN_RESET 0x00000000
|
||||
#define XCHAL_DTLB_SET5_E3_PPN_RESET 0x00000000
|
||||
|
||||
/* DTLB way set 6 (group of ways 6 thru 6): */
|
||||
#define XCHAL_DTLB_SET6_WAY 6 /* index of first way in this way set */
|
||||
#define XCHAL_DTLB_SET6_WAYS 1 /* number of (contiguous) ways in this way set */
|
||||
#define XCHAL_DTLB_SET6_ENTRIES_LOG2 3 /* log2(number of entries in this way) */
|
||||
#define XCHAL_DTLB_SET6_ENTRIES 8 /* number of entries in this way (always a power of 2) */
|
||||
#define XCHAL_DTLB_SET6_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
|
||||
#define XCHAL_DTLB_SET6_PAGESIZES 2 /* number of supported page sizes in this way */
|
||||
#define XCHAL_DTLB_SET6_PAGESZ_BITS 1 /* number of bits to encode the page size */
|
||||
#define XCHAL_DTLB_SET6_PAGESZ_LOG2_MIN 28 /* log2(minimum supported page size) */
|
||||
#define XCHAL_DTLB_SET6_PAGESZ_LOG2_MAX 29 /* log2(maximum supported page size) */
|
||||
#define XCHAL_DTLB_SET6_PAGESZ_LOG2_LIST 29 XCHAL_SEP 28 /* list of log2(page size)s, separated by XCHAL_SEP;
|
||||
2^PAGESZ_BITS entries in list, unsupported entries are zero */
|
||||
#define XCHAL_DTLB_SET6_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */
|
||||
#define XCHAL_DTLB_SET6_VPN_CONSTMASK 0 /* constant VPN bits, not including entry index bits; 0 if all writable */
|
||||
#define XCHAL_DTLB_SET6_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */
|
||||
#define XCHAL_DTLB_SET6_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */
|
||||
#define XCHAL_DTLB_SET6_ASID_RESET 1 /* 1 if ASID reset values defined (and all writable); 0 otherwise */
|
||||
#define XCHAL_DTLB_SET6_VPN_RESET 1 /* 1 if VPN reset values defined (and all writable); 0 otherwise */
|
||||
#define XCHAL_DTLB_SET6_PPN_RESET 1 /* 1 if PPN reset values defined (and all writable); 0 otherwise */
|
||||
#define XCHAL_DTLB_SET6_CA_RESET 1 /* 1 if CA reset values defined (and all writable); 0 otherwise */
|
||||
/* Reset ASID values for each entry of DTLB way set 6 (because SET6_ASID_RESET is non-zero): */
|
||||
#define XCHAL_DTLB_SET6_E0_ASID_RESET 0x01
|
||||
#define XCHAL_DTLB_SET6_E1_ASID_RESET 0x01
|
||||
#define XCHAL_DTLB_SET6_E2_ASID_RESET 0x01
|
||||
#define XCHAL_DTLB_SET6_E3_ASID_RESET 0x01
|
||||
#define XCHAL_DTLB_SET6_E4_ASID_RESET 0x01
|
||||
#define XCHAL_DTLB_SET6_E5_ASID_RESET 0x01
|
||||
#define XCHAL_DTLB_SET6_E6_ASID_RESET 0x01
|
||||
#define XCHAL_DTLB_SET6_E7_ASID_RESET 0x01
|
||||
/* Reset VPN values for each entry of DTLB way set 6 (because SET6_VPN_RESET is non-zero): */
|
||||
#define XCHAL_DTLB_SET6_E0_VPN_RESET 0x00000000
|
||||
#define XCHAL_DTLB_SET6_E1_VPN_RESET 0x20000000
|
||||
#define XCHAL_DTLB_SET6_E2_VPN_RESET 0x40000000
|
||||
#define XCHAL_DTLB_SET6_E3_VPN_RESET 0x60000000
|
||||
#define XCHAL_DTLB_SET6_E4_VPN_RESET 0x80000000
|
||||
#define XCHAL_DTLB_SET6_E5_VPN_RESET 0xA0000000
|
||||
#define XCHAL_DTLB_SET6_E6_VPN_RESET 0xC0000000
|
||||
#define XCHAL_DTLB_SET6_E7_VPN_RESET 0xE0000000
|
||||
/* Reset PPN values for each entry of DTLB way set 6 (because SET6_PPN_RESET is non-zero): */
|
||||
#define XCHAL_DTLB_SET6_E0_PPN_RESET 0x00000000
|
||||
#define XCHAL_DTLB_SET6_E1_PPN_RESET 0x20000000
|
||||
#define XCHAL_DTLB_SET6_E2_PPN_RESET 0x40000000
|
||||
#define XCHAL_DTLB_SET6_E3_PPN_RESET 0x60000000
|
||||
#define XCHAL_DTLB_SET6_E4_PPN_RESET 0x80000000
|
||||
#define XCHAL_DTLB_SET6_E5_PPN_RESET 0xA0000000
|
||||
#define XCHAL_DTLB_SET6_E6_PPN_RESET 0xC0000000
|
||||
#define XCHAL_DTLB_SET6_E7_PPN_RESET 0xE0000000
|
||||
/* Reset CA values for each entry of DTLB way set 6 (because SET6_CA_RESET is non-zero): */
|
||||
#define XCHAL_DTLB_SET6_E0_CA_RESET 0x03
|
||||
#define XCHAL_DTLB_SET6_E1_CA_RESET 0x03
|
||||
#define XCHAL_DTLB_SET6_E2_CA_RESET 0x03
|
||||
#define XCHAL_DTLB_SET6_E3_CA_RESET 0x03
|
||||
#define XCHAL_DTLB_SET6_E4_CA_RESET 0x03
|
||||
#define XCHAL_DTLB_SET6_E5_CA_RESET 0x03
|
||||
#define XCHAL_DTLB_SET6_E6_CA_RESET 0x03
|
||||
#define XCHAL_DTLB_SET6_E7_CA_RESET 0x03
|
||||
|
||||
/* DTLB way set 7 (group of ways 7 thru 7): */
|
||||
#define XCHAL_DTLB_SET7_WAY 7 /* index of first way in this way set */
|
||||
#define XCHAL_DTLB_SET7_WAYS 1 /* number of (contiguous) ways in this way set */
|
||||
#define XCHAL_DTLB_SET7_ENTRIES_LOG2 0 /* log2(number of entries in this way) */
|
||||
#define XCHAL_DTLB_SET7_ENTRIES 1 /* number of entries in this way (always a power of 2) */
|
||||
#define XCHAL_DTLB_SET7_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
|
||||
#define XCHAL_DTLB_SET7_PAGESIZES 1 /* number of supported page sizes in this way */
|
||||
#define XCHAL_DTLB_SET7_PAGESZ_BITS 0 /* number of bits to encode the page size */
|
||||
#define XCHAL_DTLB_SET7_PAGESZ_LOG2_MIN 12 /* log2(minimum supported page size) */
|
||||
#define XCHAL_DTLB_SET7_PAGESZ_LOG2_MAX 12 /* log2(maximum supported page size) */
|
||||
#define XCHAL_DTLB_SET7_PAGESZ_LOG2_LIST 12 /* list of log2(page size)s, separated by XCHAL_SEP;
|
||||
2^PAGESZ_BITS entries in list, unsupported entries are zero */
|
||||
#define XCHAL_DTLB_SET7_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */
|
||||
#define XCHAL_DTLB_SET7_VPN_CONSTMASK 0 /* constant VPN bits, not including entry index bits; 0 if all writable */
|
||||
#define XCHAL_DTLB_SET7_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */
|
||||
#define XCHAL_DTLB_SET7_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */
|
||||
#define XCHAL_DTLB_SET7_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */
|
||||
#define XCHAL_DTLB_SET7_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */
|
||||
#define XCHAL_DTLB_SET7_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */
|
||||
#define XCHAL_DTLB_SET7_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */
|
||||
|
||||
/* DTLB way set 8 (group of ways 8 thru 8): */
|
||||
#define XCHAL_DTLB_SET8_WAY 8 /* index of first way in this way set */
|
||||
#define XCHAL_DTLB_SET8_WAYS 1 /* number of (contiguous) ways in this way set */
|
||||
#define XCHAL_DTLB_SET8_ENTRIES_LOG2 0 /* log2(number of entries in this way) */
|
||||
#define XCHAL_DTLB_SET8_ENTRIES 1 /* number of entries in this way (always a power of 2) */
|
||||
#define XCHAL_DTLB_SET8_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
|
||||
#define XCHAL_DTLB_SET8_PAGESIZES 1 /* number of supported page sizes in this way */
|
||||
#define XCHAL_DTLB_SET8_PAGESZ_BITS 0 /* number of bits to encode the page size */
|
||||
#define XCHAL_DTLB_SET8_PAGESZ_LOG2_MIN 12 /* log2(minimum supported page size) */
|
||||
#define XCHAL_DTLB_SET8_PAGESZ_LOG2_MAX 12 /* log2(maximum supported page size) */
|
||||
#define XCHAL_DTLB_SET8_PAGESZ_LOG2_LIST 12 /* list of log2(page size)s, separated by XCHAL_SEP;
|
||||
2^PAGESZ_BITS entries in list, unsupported entries are zero */
|
||||
#define XCHAL_DTLB_SET8_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */
|
||||
#define XCHAL_DTLB_SET8_VPN_CONSTMASK 0 /* constant VPN bits, not including entry index bits; 0 if all writable */
|
||||
#define XCHAL_DTLB_SET8_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */
|
||||
#define XCHAL_DTLB_SET8_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */
|
||||
#define XCHAL_DTLB_SET8_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */
|
||||
#define XCHAL_DTLB_SET8_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */
|
||||
#define XCHAL_DTLB_SET8_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */
|
||||
#define XCHAL_DTLB_SET8_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */
|
||||
|
||||
/* DTLB way set 9 (group of ways 9 thru 9): */
|
||||
#define XCHAL_DTLB_SET9_WAY 9 /* index of first way in this way set */
|
||||
#define XCHAL_DTLB_SET9_WAYS 1 /* number of (contiguous) ways in this way set */
|
||||
#define XCHAL_DTLB_SET9_ENTRIES_LOG2 0 /* log2(number of entries in this way) */
|
||||
#define XCHAL_DTLB_SET9_ENTRIES 1 /* number of entries in this way (always a power of 2) */
|
||||
#define XCHAL_DTLB_SET9_ARF 0 /* 1=autorefill by h/w, 0=non-autorefill (wired/constant/static) */
|
||||
#define XCHAL_DTLB_SET9_PAGESIZES 1 /* number of supported page sizes in this way */
|
||||
#define XCHAL_DTLB_SET9_PAGESZ_BITS 0 /* number of bits to encode the page size */
|
||||
#define XCHAL_DTLB_SET9_PAGESZ_LOG2_MIN 12 /* log2(minimum supported page size) */
|
||||
#define XCHAL_DTLB_SET9_PAGESZ_LOG2_MAX 12 /* log2(maximum supported page size) */
|
||||
#define XCHAL_DTLB_SET9_PAGESZ_LOG2_LIST 12 /* list of log2(page size)s, separated by XCHAL_SEP;
|
||||
2^PAGESZ_BITS entries in list, unsupported entries are zero */
|
||||
#define XCHAL_DTLB_SET9_ASID_CONSTMASK 0 /* constant ASID bits; 0 if all writable */
|
||||
#define XCHAL_DTLB_SET9_VPN_CONSTMASK 0 /* constant VPN bits, not including entry index bits; 0 if all writable */
|
||||
#define XCHAL_DTLB_SET9_PPN_CONSTMASK 0 /* constant PPN bits, including entry index bits; 0 if all writable */
|
||||
#define XCHAL_DTLB_SET9_CA_CONSTMASK 0 /* constant CA bits; 0 if all writable */
|
||||
#define XCHAL_DTLB_SET9_ASID_RESET 0 /* 1 if ASID reset values defined (and all writable); 0 otherwise */
|
||||
#define XCHAL_DTLB_SET9_VPN_RESET 0 /* 1 if VPN reset values defined (and all writable); 0 otherwise */
|
||||
#define XCHAL_DTLB_SET9_PPN_RESET 0 /* 1 if PPN reset values defined (and all writable); 0 otherwise */
|
||||
#define XCHAL_DTLB_SET9_CA_RESET 0 /* 1 if CA reset values defined (and all writable); 0 otherwise */
|
||||
|
||||
|
||||
|
||||
|
||||
#endif /*XTENSA_CONFIG_CORE_MATMAP_H*/
|
||||
|
||||
277
target/xtensa/core-de233_fpu/gdb-config.c.inc
Normal file
277
target/xtensa/core-de233_fpu/gdb-config.c.inc
Normal file
@ -0,0 +1,277 @@
|
||||
/* Configuration for the Xtensa architecture for GDB, the GNU debugger.
|
||||
|
||||
Copyright (c) 2003-2020 Tensilica Inc.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining
|
||||
a copy of this software and associated documentation files (the
|
||||
"Software"), to deal in the Software without restriction, including
|
||||
without limitation the rights to use, copy, modify, merge, publish,
|
||||
distribute, sublicense, and/or sell copies of the Software, and to
|
||||
permit persons to whom the Software is furnished to do so, subject to
|
||||
the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included
|
||||
in all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
|
||||
IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
|
||||
CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
|
||||
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
|
||||
XTREG( 0, 0,32, 4, 4,0x0020,0x0006,-2, 9,0x2100,pc, 0,0,0,0,0,0)
|
||||
XTREG( 1, 4,32, 4, 4,0x0100,0x0006,-2, 1,0x0002,ar0, 0,0,0,0,0,0)
|
||||
XTREG( 2, 8,32, 4, 4,0x0101,0x0006,-2, 1,0x0002,ar1, 0,0,0,0,0,0)
|
||||
XTREG( 3, 12,32, 4, 4,0x0102,0x0006,-2, 1,0x0002,ar2, 0,0,0,0,0,0)
|
||||
XTREG( 4, 16,32, 4, 4,0x0103,0x0006,-2, 1,0x0002,ar3, 0,0,0,0,0,0)
|
||||
XTREG( 5, 20,32, 4, 4,0x0104,0x0006,-2, 1,0x0002,ar4, 0,0,0,0,0,0)
|
||||
XTREG( 6, 24,32, 4, 4,0x0105,0x0006,-2, 1,0x0002,ar5, 0,0,0,0,0,0)
|
||||
XTREG( 7, 28,32, 4, 4,0x0106,0x0006,-2, 1,0x0002,ar6, 0,0,0,0,0,0)
|
||||
XTREG( 8, 32,32, 4, 4,0x0107,0x0006,-2, 1,0x0002,ar7, 0,0,0,0,0,0)
|
||||
XTREG( 9, 36,32, 4, 4,0x0108,0x0006,-2, 1,0x0002,ar8, 0,0,0,0,0,0)
|
||||
XTREG( 10, 40,32, 4, 4,0x0109,0x0006,-2, 1,0x0002,ar9, 0,0,0,0,0,0)
|
||||
XTREG( 11, 44,32, 4, 4,0x010a,0x0006,-2, 1,0x0002,ar10, 0,0,0,0,0,0)
|
||||
XTREG( 12, 48,32, 4, 4,0x010b,0x0006,-2, 1,0x0002,ar11, 0,0,0,0,0,0)
|
||||
XTREG( 13, 52,32, 4, 4,0x010c,0x0006,-2, 1,0x0002,ar12, 0,0,0,0,0,0)
|
||||
XTREG( 14, 56,32, 4, 4,0x010d,0x0006,-2, 1,0x0002,ar13, 0,0,0,0,0,0)
|
||||
XTREG( 15, 60,32, 4, 4,0x010e,0x0006,-2, 1,0x0002,ar14, 0,0,0,0,0,0)
|
||||
XTREG( 16, 64,32, 4, 4,0x010f,0x0006,-2, 1,0x0002,ar15, 0,0,0,0,0,0)
|
||||
XTREG( 17, 68,32, 4, 4,0x0110,0x0006,-2, 1,0x0002,ar16, 0,0,0,0,0,0)
|
||||
XTREG( 18, 72,32, 4, 4,0x0111,0x0006,-2, 1,0x0002,ar17, 0,0,0,0,0,0)
|
||||
XTREG( 19, 76,32, 4, 4,0x0112,0x0006,-2, 1,0x0002,ar18, 0,0,0,0,0,0)
|
||||
XTREG( 20, 80,32, 4, 4,0x0113,0x0006,-2, 1,0x0002,ar19, 0,0,0,0,0,0)
|
||||
XTREG( 21, 84,32, 4, 4,0x0114,0x0006,-2, 1,0x0002,ar20, 0,0,0,0,0,0)
|
||||
XTREG( 22, 88,32, 4, 4,0x0115,0x0006,-2, 1,0x0002,ar21, 0,0,0,0,0,0)
|
||||
XTREG( 23, 92,32, 4, 4,0x0116,0x0006,-2, 1,0x0002,ar22, 0,0,0,0,0,0)
|
||||
XTREG( 24, 96,32, 4, 4,0x0117,0x0006,-2, 1,0x0002,ar23, 0,0,0,0,0,0)
|
||||
XTREG( 25,100,32, 4, 4,0x0118,0x0006,-2, 1,0x0002,ar24, 0,0,0,0,0,0)
|
||||
XTREG( 26,104,32, 4, 4,0x0119,0x0006,-2, 1,0x0002,ar25, 0,0,0,0,0,0)
|
||||
XTREG( 27,108,32, 4, 4,0x011a,0x0006,-2, 1,0x0002,ar26, 0,0,0,0,0,0)
|
||||
XTREG( 28,112,32, 4, 4,0x011b,0x0006,-2, 1,0x0002,ar27, 0,0,0,0,0,0)
|
||||
XTREG( 29,116,32, 4, 4,0x011c,0x0006,-2, 1,0x0002,ar28, 0,0,0,0,0,0)
|
||||
XTREG( 30,120,32, 4, 4,0x011d,0x0006,-2, 1,0x0002,ar29, 0,0,0,0,0,0)
|
||||
XTREG( 31,124,32, 4, 4,0x011e,0x0006,-2, 1,0x0002,ar30, 0,0,0,0,0,0)
|
||||
XTREG( 32,128,32, 4, 4,0x011f,0x0006,-2, 1,0x0002,ar31, 0,0,0,0,0,0)
|
||||
XTREG( 33,132,32, 4, 4,0x0200,0x0006,-2, 2,0x1100,lbeg, 0,0,0,0,0,0)
|
||||
XTREG( 34,136,32, 4, 4,0x0201,0x0006,-2, 2,0x1100,lend, 0,0,0,0,0,0)
|
||||
XTREG( 35,140,32, 4, 4,0x0202,0x0006,-2, 2,0x1100,lcount, 0,0,0,0,0,0)
|
||||
XTREG( 36,144, 6, 4, 4,0x0203,0x0006,-2, 2,0x1100,sar, 0,0,0,0,0,0)
|
||||
XTREG( 37,148, 3, 4, 4,0x0248,0x0006,-2, 2,0x1002,windowbase, 0,0,0,0,0,0)
|
||||
XTREG( 38,152, 8, 4, 4,0x0249,0x0006,-2, 2,0x1002,windowstart, 0,0,0,0,0,0)
|
||||
XTREG( 39,156,32, 4, 4,0x02b0,0x0002,-2, 2,0x1000,configid0, 0,0,0,0,0,0)
|
||||
XTREG( 40,160,32, 4, 4,0x02d0,0x0002,-2, 2,0x1000,configid1, 0,0,0,0,0,0)
|
||||
XTREG( 41,164,19, 4, 4,0x02e6,0x0006,-2, 2,0x1100,ps, 0,0,0,0,0,0)
|
||||
XTREG( 42,168,32, 4, 4,0x03e7,0x0006,-2, 3,0x0110,threadptr, 0,0,0,0,0,0)
|
||||
XTREG( 43,172,16, 4, 4,0x0204,0x0006,-1, 2,0x1100,br, 0,0,0,0,0,0)
|
||||
XTREG( 44,176,32, 4, 4,0x020c,0x0006,-1, 2,0x1100,scompare1, 0,0,0,0,0,0)
|
||||
XTREG( 45,180,32, 4, 4,0x0210,0x0006,-1, 2,0x1100,acclo, 0,0,0,0,0,0)
|
||||
XTREG( 46,184, 8, 4, 4,0x0211,0x0006,-1, 2,0x1100,acchi, 0,0,0,0,0,0)
|
||||
XTREG( 47,188,32, 4, 4,0x0220,0x0006,-1, 2,0x1100,m0, 0,0,0,0,0,0)
|
||||
XTREG( 48,192,32, 4, 4,0x0221,0x0006,-1, 2,0x1100,m1, 0,0,0,0,0,0)
|
||||
XTREG( 49,196,32, 4, 4,0x0222,0x0006,-1, 2,0x1100,m2, 0,0,0,0,0,0)
|
||||
XTREG( 50,200,32, 4, 4,0x0223,0x0006,-1, 2,0x1100,m3, 0,0,0,0,0,0)
|
||||
XTREG( 51,204,32, 4, 4,0x03e6,0x000e,-1, 3,0x0110,expstate, 0,0,0,0,0,0)
|
||||
XTREG( 52,208,64, 8, 8,0x0030,0x0006, 0, 4,0x0401,f0,
|
||||
"03:03:54:00","03:03:14:00",0,0,0,0)
|
||||
XTREG( 53,216,64, 8, 8,0x0031,0x0006, 0, 4,0x0401,f1,
|
||||
"03:13:54:00","03:13:14:00",0,0,0,0)
|
||||
XTREG( 54,224,64, 8, 8,0x0032,0x0006, 0, 4,0x0401,f2,
|
||||
"03:23:54:00","03:23:14:00",0,0,0,0)
|
||||
XTREG( 55,232,64, 8, 8,0x0033,0x0006, 0, 4,0x0401,f3,
|
||||
"03:33:54:00","03:33:14:00",0,0,0,0)
|
||||
XTREG( 56,240,64, 8, 8,0x0034,0x0006, 0, 4,0x0401,f4,
|
||||
"03:43:54:00","03:43:14:00",0,0,0,0)
|
||||
XTREG( 57,248,64, 8, 8,0x0035,0x0006, 0, 4,0x0401,f5,
|
||||
"03:53:54:00","03:53:14:00",0,0,0,0)
|
||||
XTREG( 58,256,64, 8, 8,0x0036,0x0006, 0, 4,0x0401,f6,
|
||||
"03:63:54:00","03:63:14:00",0,0,0,0)
|
||||
XTREG( 59,264,64, 8, 8,0x0037,0x0006, 0, 4,0x0401,f7,
|
||||
"03:73:54:00","03:73:14:00",0,0,0,0)
|
||||
XTREG( 60,272,64, 8, 8,0x0038,0x0006, 0, 4,0x0401,f8,
|
||||
"03:83:54:00","03:83:14:00",0,0,0,0)
|
||||
XTREG( 61,280,64, 8, 8,0x0039,0x0006, 0, 4,0x0401,f9,
|
||||
"03:93:54:00","03:93:14:00",0,0,0,0)
|
||||
XTREG( 62,288,64, 8, 8,0x003a,0x0006, 0, 4,0x0401,f10,
|
||||
"03:a3:54:00","03:a3:14:00",0,0,0,0)
|
||||
XTREG( 63,296,64, 8, 8,0x003b,0x0006, 0, 4,0x0401,f11,
|
||||
"03:b3:54:00","03:b3:14:00",0,0,0,0)
|
||||
XTREG( 64,304,64, 8, 8,0x003c,0x0006, 0, 4,0x0401,f12,
|
||||
"03:c3:54:00","03:c3:14:00",0,0,0,0)
|
||||
XTREG( 65,312,64, 8, 8,0x003d,0x0006, 0, 4,0x0401,f13,
|
||||
"03:d3:54:00","03:d3:14:00",0,0,0,0)
|
||||
XTREG( 66,320,64, 8, 8,0x003e,0x0006, 0, 4,0x0401,f14,
|
||||
"03:e3:54:00","03:e3:14:00",0,0,0,0)
|
||||
XTREG( 67,328,64, 8, 8,0x003f,0x0006, 0, 4,0x0401,f15,
|
||||
"03:f3:54:00","03:f3:14:00",0,0,0,0)
|
||||
XTREG( 68,336,32, 4, 4,0x03e8,0x0006, 0, 3,0x0100,fcr, 0,0,0,0,0,0)
|
||||
XTREG( 69,340,32, 4, 4,0x03e9,0x0006, 0, 3,0x0100,fsr, 0,0,0,0,0,0)
|
||||
XTREG( 70,344,32, 4, 4,0x0253,0x0007,-2, 2,0x1000,ptevaddr, 0,0,0,0,0,0)
|
||||
XTREG( 71,348,32, 4, 4,0x0259,0x000d,-2, 2,0x1000,mmid, 0,0,0,0,0,0)
|
||||
XTREG( 72,352,32, 4, 4,0x025a,0x0007,-2, 2,0x1000,rasid, 0,0,0,0,0,0)
|
||||
XTREG( 73,356,25, 4, 4,0x025b,0x0007,-2, 2,0x1000,itlbcfg, 0,0,0,0,0,0)
|
||||
XTREG( 74,360,25, 4, 4,0x025c,0x0007,-2, 2,0x1000,dtlbcfg, 0,0,0,0,0,0)
|
||||
XTREG( 75,364,16, 4, 4,0x025f,0x0007,-2, 2,0x1000,eraccess, 0,0,0,0,0,0)
|
||||
XTREG( 76,368, 2, 4, 4,0x0260,0x0007,-2, 2,0x1000,ibreakenable,0,0,0,0,0,0)
|
||||
XTREG( 77,372, 6, 4, 4,0x0263,0x0007,-2, 2,0x1000,atomctl, 0,0,0,0,0,0)
|
||||
XTREG( 78,376,32, 4, 4,0x0268,0x0007,-2, 2,0x1000,ddr, 0,0,0,0,0,0)
|
||||
XTREG( 79,380,32, 4, 4,0x0280,0x0007,-2, 2,0x1000,ibreaka0, 0,0,0,0,0,0)
|
||||
XTREG( 80,384,32, 4, 4,0x0281,0x0007,-2, 2,0x1000,ibreaka1, 0,0,0,0,0,0)
|
||||
XTREG( 81,388,32, 4, 4,0x0290,0x0007,-2, 2,0x1000,dbreaka0, 0,0,0,0,0,0)
|
||||
XTREG( 82,392,32, 4, 4,0x0291,0x0007,-2, 2,0x1000,dbreaka1, 0,0,0,0,0,0)
|
||||
XTREG( 83,396,32, 4, 4,0x02a0,0x0007,-2, 2,0x1000,dbreakc0, 0,0,0,0,0,0)
|
||||
XTREG( 84,400,32, 4, 4,0x02a1,0x0007,-2, 2,0x1000,dbreakc1, 0,0,0,0,0,0)
|
||||
XTREG( 85,404,32, 4, 4,0x02b1,0x0007,-2, 2,0x1000,epc1, 0,0,0,0,0,0)
|
||||
XTREG( 86,408,32, 4, 4,0x02b2,0x0007,-2, 2,0x1000,epc2, 0,0,0,0,0,0)
|
||||
XTREG( 87,412,32, 4, 4,0x02b3,0x0007,-2, 2,0x1000,epc3, 0,0,0,0,0,0)
|
||||
XTREG( 88,416,32, 4, 4,0x02b4,0x0007,-2, 2,0x1000,epc4, 0,0,0,0,0,0)
|
||||
XTREG( 89,420,32, 4, 4,0x02b5,0x0007,-2, 2,0x1000,epc5, 0,0,0,0,0,0)
|
||||
XTREG( 90,424,32, 4, 4,0x02b6,0x0007,-2, 2,0x1000,epc6, 0,0,0,0,0,0)
|
||||
XTREG( 91,428,32, 4, 4,0x02b7,0x0007,-2, 2,0x1000,epc7, 0,0,0,0,0,0)
|
||||
XTREG( 92,432,32, 4, 4,0x02c0,0x0007,-2, 2,0x1000,depc, 0,0,0,0,0,0)
|
||||
XTREG( 93,436,19, 4, 4,0x02c2,0x0007,-2, 2,0x1000,eps2, 0,0,0,0,0,0)
|
||||
XTREG( 94,440,19, 4, 4,0x02c3,0x0007,-2, 2,0x1000,eps3, 0,0,0,0,0,0)
|
||||
XTREG( 95,444,19, 4, 4,0x02c4,0x0007,-2, 2,0x1000,eps4, 0,0,0,0,0,0)
|
||||
XTREG( 96,448,19, 4, 4,0x02c5,0x0007,-2, 2,0x1000,eps5, 0,0,0,0,0,0)
|
||||
XTREG( 97,452,19, 4, 4,0x02c6,0x0007,-2, 2,0x1000,eps6, 0,0,0,0,0,0)
|
||||
XTREG( 98,456,19, 4, 4,0x02c7,0x0007,-2, 2,0x1000,eps7, 0,0,0,0,0,0)
|
||||
XTREG( 99,460,32, 4, 4,0x02d1,0x0007,-2, 2,0x1000,excsave1, 0,0,0,0,0,0)
|
||||
XTREG(100,464,32, 4, 4,0x02d2,0x0007,-2, 2,0x1000,excsave2, 0,0,0,0,0,0)
|
||||
XTREG(101,468,32, 4, 4,0x02d3,0x0007,-2, 2,0x1000,excsave3, 0,0,0,0,0,0)
|
||||
XTREG(102,472,32, 4, 4,0x02d4,0x0007,-2, 2,0x1000,excsave4, 0,0,0,0,0,0)
|
||||
XTREG(103,476,32, 4, 4,0x02d5,0x0007,-2, 2,0x1000,excsave5, 0,0,0,0,0,0)
|
||||
XTREG(104,480,32, 4, 4,0x02d6,0x0007,-2, 2,0x1000,excsave6, 0,0,0,0,0,0)
|
||||
XTREG(105,484,32, 4, 4,0x02d7,0x0007,-2, 2,0x1000,excsave7, 0,0,0,0,0,0)
|
||||
XTREG(106,488, 8, 4, 4,0x02e0,0x0007,-2, 2,0x1000,cpenable, 0,0,0,0,0,0)
|
||||
XTREG(107,492,22, 4, 4,0x02e2,0x000b,-2, 2,0x1000,interrupt, 0,0,0,0,0,0)
|
||||
XTREG(108,496,22, 4, 4,0x02e2,0x000d,-2, 2,0x1000,intset, 0,0,0,0,0,0)
|
||||
XTREG(109,500,22, 4, 4,0x02e3,0x000d,-2, 2,0x1000,intclear, 0,0,0,0,0,0)
|
||||
XTREG(110,504,22, 4, 4,0x02e4,0x0007,-2, 2,0x1000,intenable, 0,0,0,0,0,0)
|
||||
XTREG(111,508,32, 4, 4,0x02e7,0x0007,-2, 2,0x1000,vecbase, 0,0,0,0,0,0)
|
||||
XTREG(112,512, 6, 4, 4,0x02e8,0x0007,-2, 2,0x1000,exccause, 0,0,0,0,0,0)
|
||||
XTREG(113,516,12, 4, 4,0x02e9,0x0003,-2, 2,0x1000,debugcause, 0,0,0,0,0,0)
|
||||
XTREG(114,520,32, 4, 4,0x02ea,0x000f,-2, 2,0x1000,ccount, 0,0,0,0,0,0)
|
||||
XTREG(115,524,32, 4, 4,0x02eb,0x0003,-2, 2,0x1000,prid, 0,0,0,0,0,0)
|
||||
XTREG(116,528,32, 4, 4,0x02ec,0x000f,-2, 2,0x1000,icount, 0,0,0,0,0,0)
|
||||
XTREG(117,532, 4, 4, 4,0x02ed,0x0007,-2, 2,0x1000,icountlevel, 0,0,0,0,0,0)
|
||||
XTREG(118,536,32, 4, 4,0x02ee,0x0007,-2, 2,0x1000,excvaddr, 0,0,0,0,0,0)
|
||||
XTREG(119,540,32, 4, 4,0x02f0,0x000f,-2, 2,0x1000,ccompare0, 0,0,0,0,0,0)
|
||||
XTREG(120,544,32, 4, 4,0x02f1,0x000f,-2, 2,0x1000,ccompare1, 0,0,0,0,0,0)
|
||||
XTREG(121,548,32, 4, 4,0x02f2,0x000f,-2, 2,0x1000,ccompare2, 0,0,0,0,0,0)
|
||||
XTREG(122,552,32, 4, 4,0x02f4,0x0007,-2, 2,0x1000,misc0, 0,0,0,0,0,0)
|
||||
XTREG(123,556,32, 4, 4,0x02f5,0x0007,-2, 2,0x1000,misc1, 0,0,0,0,0,0)
|
||||
XTREG(124,560,32, 4, 4,0x0000,0x0006,-2, 8,0x2100,a0, 0,0,0,0,0,0)
|
||||
XTREG(125,564,32, 4, 4,0x0001,0x0006,-2, 8,0x2100,a1, 0,0,0,0,0,0)
|
||||
XTREG(126,568,32, 4, 4,0x0002,0x0006,-2, 8,0x2100,a2, 0,0,0,0,0,0)
|
||||
XTREG(127,572,32, 4, 4,0x0003,0x0006,-2, 8,0x2100,a3, 0,0,0,0,0,0)
|
||||
XTREG(128,576,32, 4, 4,0x0004,0x0006,-2, 8,0x2100,a4, 0,0,0,0,0,0)
|
||||
XTREG(129,580,32, 4, 4,0x0005,0x0006,-2, 8,0x2100,a5, 0,0,0,0,0,0)
|
||||
XTREG(130,584,32, 4, 4,0x0006,0x0006,-2, 8,0x2100,a6, 0,0,0,0,0,0)
|
||||
XTREG(131,588,32, 4, 4,0x0007,0x0006,-2, 8,0x2100,a7, 0,0,0,0,0,0)
|
||||
XTREG(132,592,32, 4, 4,0x0008,0x0006,-2, 8,0x2100,a8, 0,0,0,0,0,0)
|
||||
XTREG(133,596,32, 4, 4,0x0009,0x0006,-2, 8,0x2100,a9, 0,0,0,0,0,0)
|
||||
XTREG(134,600,32, 4, 4,0x000a,0x0006,-2, 8,0x2100,a10, 0,0,0,0,0,0)
|
||||
XTREG(135,604,32, 4, 4,0x000b,0x0006,-2, 8,0x2100,a11, 0,0,0,0,0,0)
|
||||
XTREG(136,608,32, 4, 4,0x000c,0x0006,-2, 8,0x2100,a12, 0,0,0,0,0,0)
|
||||
XTREG(137,612,32, 4, 4,0x000d,0x0006,-2, 8,0x2100,a13, 0,0,0,0,0,0)
|
||||
XTREG(138,616,32, 4, 4,0x000e,0x0006,-2, 8,0x2100,a14, 0,0,0,0,0,0)
|
||||
XTREG(139,620,32, 4, 4,0x000f,0x0006,-2, 8,0x2100,a15, 0,0,0,0,0,0)
|
||||
XTREG(140,624, 1, 1, 1,0x0010,0x0006,-2, 6,0x1010,b0,
|
||||
0,0,&xtensa_mask0,0,0,0)
|
||||
XTREG(141,625, 1, 1, 1,0x0011,0x0006,-2, 6,0x1010,b1,
|
||||
0,0,&xtensa_mask1,0,0,0)
|
||||
XTREG(142,626, 1, 1, 1,0x0012,0x0006,-2, 6,0x1010,b2,
|
||||
0,0,&xtensa_mask2,0,0,0)
|
||||
XTREG(143,627, 1, 1, 1,0x0013,0x0006,-2, 6,0x1010,b3,
|
||||
0,0,&xtensa_mask3,0,0,0)
|
||||
XTREG(144,628, 1, 1, 1,0x0014,0x0006,-2, 6,0x1010,b4,
|
||||
0,0,&xtensa_mask4,0,0,0)
|
||||
XTREG(145,629, 1, 1, 1,0x0015,0x0006,-2, 6,0x1010,b5,
|
||||
0,0,&xtensa_mask5,0,0,0)
|
||||
XTREG(146,630, 1, 1, 1,0x0016,0x0006,-2, 6,0x1010,b6,
|
||||
0,0,&xtensa_mask6,0,0,0)
|
||||
XTREG(147,631, 1, 1, 1,0x0017,0x0006,-2, 6,0x1010,b7,
|
||||
0,0,&xtensa_mask7,0,0,0)
|
||||
XTREG(148,632, 1, 1, 1,0x0018,0x0006,-2, 6,0x1010,b8,
|
||||
0,0,&xtensa_mask8,0,0,0)
|
||||
XTREG(149,633, 1, 1, 1,0x0019,0x0006,-2, 6,0x1010,b9,
|
||||
0,0,&xtensa_mask9,0,0,0)
|
||||
XTREG(150,634, 1, 1, 1,0x001a,0x0006,-2, 6,0x1010,b10,
|
||||
0,0,&xtensa_mask10,0,0,0)
|
||||
XTREG(151,635, 1, 1, 1,0x001b,0x0006,-2, 6,0x1010,b11,
|
||||
0,0,&xtensa_mask11,0,0,0)
|
||||
XTREG(152,636, 1, 1, 1,0x001c,0x0006,-2, 6,0x1010,b12,
|
||||
0,0,&xtensa_mask12,0,0,0)
|
||||
XTREG(153,637, 1, 1, 1,0x001d,0x0006,-2, 6,0x1010,b13,
|
||||
0,0,&xtensa_mask13,0,0,0)
|
||||
XTREG(154,638, 1, 1, 1,0x001e,0x0006,-2, 6,0x1010,b14,
|
||||
0,0,&xtensa_mask14,0,0,0)
|
||||
XTREG(155,639, 1, 1, 1,0x001f,0x0006,-2, 6,0x1010,b15,
|
||||
0,0,&xtensa_mask15,0,0,0)
|
||||
XTREG(156,640, 4, 4, 4,0x2008,0x0006,-2, 6,0x1010,psintlevel,
|
||||
0,0,&xtensa_mask16,0,0,0)
|
||||
XTREG(157,644, 1, 4, 4,0x2009,0x0006,-2, 6,0x1010,psum,
|
||||
0,0,&xtensa_mask17,0,0,0)
|
||||
XTREG(158,648, 1, 4, 4,0x200a,0x0006,-2, 6,0x1010,pswoe,
|
||||
0,0,&xtensa_mask18,0,0,0)
|
||||
XTREG(159,652, 2, 4, 4,0x200b,0x0006,-2, 6,0x1010,psring,
|
||||
0,0,&xtensa_mask19,0,0,0)
|
||||
XTREG(160,656, 1, 4, 4,0x200c,0x0006,-2, 6,0x1010,psexcm,
|
||||
0,0,&xtensa_mask20,0,0,0)
|
||||
XTREG(161,660, 2, 4, 4,0x200d,0x0006,-2, 6,0x1010,pscallinc,
|
||||
0,0,&xtensa_mask21,0,0,0)
|
||||
XTREG(162,664, 4, 4, 4,0x200e,0x0006,-2, 6,0x1010,psowb,
|
||||
0,0,&xtensa_mask22,0,0,0)
|
||||
XTREG(163,668,40, 8, 4,0x200f,0x0006,-2, 6,0x1010,acc,
|
||||
0,0,&xtensa_mask23,0,0,0)
|
||||
XTREG(164,676, 4, 4, 4,0x2014,0x0006,-2, 6,0x1010,dbnum,
|
||||
0,0,&xtensa_mask24,0,0,0)
|
||||
XTREG(165,680, 8, 4, 4,0x2015,0x0006,-2, 6,0x1010,asid3,
|
||||
0,0,&xtensa_mask25,0,0,0)
|
||||
XTREG(166,684, 8, 4, 4,0x2016,0x0006,-2, 6,0x1010,asid2,
|
||||
0,0,&xtensa_mask26,0,0,0)
|
||||
XTREG(167,688, 8, 4, 4,0x2017,0x0006,-2, 6,0x1010,asid1,
|
||||
0,0,&xtensa_mask27,0,0,0)
|
||||
XTREG(168,692, 1, 4, 4,0x2018,0x0006,-2, 6,0x1010,instpgszid6,
|
||||
0,0,&xtensa_mask28,0,0,0)
|
||||
XTREG(169,696, 1, 4, 4,0x2019,0x0006,-2, 6,0x1010,instpgszid5,
|
||||
0,0,&xtensa_mask29,0,0,0)
|
||||
XTREG(170,700, 2, 4, 4,0x201a,0x0006,-2, 6,0x1010,instpgszid4,
|
||||
0,0,&xtensa_mask30,0,0,0)
|
||||
XTREG(171,704, 1, 4, 4,0x201b,0x0006,-2, 6,0x1010,datapgszid6,
|
||||
0,0,&xtensa_mask31,0,0,0)
|
||||
XTREG(172,708, 1, 4, 4,0x201c,0x0006,-2, 6,0x1010,datapgszid5,
|
||||
0,0,&xtensa_mask32,0,0,0)
|
||||
XTREG(173,712, 2, 4, 4,0x201d,0x0006,-2, 6,0x1010,datapgszid4,
|
||||
0,0,&xtensa_mask33,0,0,0)
|
||||
XTREG(174,716,10, 4, 4,0x201e,0x0006,-2, 6,0x1010,ptbase,
|
||||
0,0,&xtensa_mask34,0,0,0)
|
||||
XTREG(175,720, 2, 4, 4,0x201f,0x0006, 0, 5,0x1010,roundmode,
|
||||
0,0,&xtensa_mask35,0,0,0)
|
||||
XTREG(176,724, 1, 4, 4,0x2020,0x0006, 0, 5,0x1010,invalidenable,
|
||||
0,0,&xtensa_mask36,0,0,0)
|
||||
XTREG(177,728, 1, 4, 4,0x2021,0x0006, 0, 5,0x1010,divzeroenable,
|
||||
0,0,&xtensa_mask37,0,0,0)
|
||||
XTREG(178,732, 1, 4, 4,0x2022,0x0006, 0, 5,0x1010,overflowenable,
|
||||
0,0,&xtensa_mask38,0,0,0)
|
||||
XTREG(179,736, 1, 4, 4,0x2023,0x0006, 0, 5,0x1010,underflowenable,
|
||||
0,0,&xtensa_mask39,0,0,0)
|
||||
XTREG(180,740, 1, 4, 4,0x2024,0x0006, 0, 5,0x1010,inexactenable,
|
||||
0,0,&xtensa_mask40,0,0,0)
|
||||
XTREG(181,744, 1, 4, 4,0x2025,0x0006, 0, 5,0x1010,invalidflag,
|
||||
0,0,&xtensa_mask41,0,0,0)
|
||||
XTREG(182,748, 1, 4, 4,0x2026,0x0006, 0, 5,0x1010,divzeroflag,
|
||||
0,0,&xtensa_mask42,0,0,0)
|
||||
XTREG(183,752, 1, 4, 4,0x2027,0x0006, 0, 5,0x1010,overflowflag,
|
||||
0,0,&xtensa_mask43,0,0,0)
|
||||
XTREG(184,756, 1, 4, 4,0x2028,0x0006, 0, 5,0x1010,underflowflag,
|
||||
0,0,&xtensa_mask44,0,0,0)
|
||||
XTREG(185,760, 1, 4, 4,0x2029,0x0006, 0, 5,0x1010,inexactflag,
|
||||
0,0,&xtensa_mask45,0,0,0)
|
||||
XTREG(186,764,20, 4, 4,0x202a,0x0006, 0, 5,0x1010,fpreserved20,
|
||||
0,0,&xtensa_mask46,0,0,0)
|
||||
XTREG(187,768,20, 4, 4,0x202b,0x0006, 0, 5,0x1010,fpreserved20a,
|
||||
0,0,&xtensa_mask47,0,0,0)
|
||||
XTREG(188,772, 5, 4, 4,0x202c,0x0006, 0, 5,0x1010,fpreserved5,
|
||||
0,0,&xtensa_mask48,0,0,0)
|
||||
XTREG_END
|
||||
20758
target/xtensa/core-de233_fpu/xtensa-modules.c.inc
Normal file
20758
target/xtensa/core-de233_fpu/xtensa-modules.c.inc
Normal file
File diff suppressed because it is too large
Load Diff
@ -3,6 +3,7 @@ xtensa_ss.add(files(
|
||||
'core-dc232b.c',
|
||||
'core-dc233c.c',
|
||||
'core-de212.c',
|
||||
'core-de233_fpu.c',
|
||||
'core-fsf.c',
|
||||
'core-sample_controller.c',
|
||||
'core-test_kc705_be.c',
|
||||
|
||||
Loading…
Reference in New Issue
Block a user