target-sh4: cleanup DisasContext
We should avoid accessing env at translation stage, except of course for static values like the supported features. Remove variables copied from env in DisasContext and use the TB flags instead. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
This commit is contained in:
Aurelien Jarno
parent
1012740098
commit
7a64244fda
@ -32,8 +32,6 @@
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typedef struct DisasContext {
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struct TranslationBlock *tb;
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target_ulong pc;
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uint32_t sr;
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uint32_t fpscr;
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uint16_t opcode;
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uint32_t flags;
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int bstate;
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@ -47,7 +45,7 @@ typedef struct DisasContext {
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#if defined(CONFIG_USER_ONLY)
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#define IS_USER(ctx) 1
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#else
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#define IS_USER(ctx) (!(ctx->sr & SR_MD))
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#define IS_USER(ctx) (!(ctx->flags & SR_MD))
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#endif
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enum {
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@ -413,15 +411,15 @@ static inline void gen_store_fpr64 (TCGv_i64 t, int reg)
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#define B11_8 ((ctx->opcode >> 8) & 0xf)
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#define B15_12 ((ctx->opcode >> 12) & 0xf)
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#define REG(x) ((x) < 8 && (ctx->sr & (SR_MD | SR_RB)) == (SR_MD | SR_RB) ? \
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(cpu_gregs[x + 16]) : (cpu_gregs[x]))
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#define REG(x) ((x) < 8 && (ctx->flags & (SR_MD | SR_RB)) == (SR_MD | SR_RB) \
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? (cpu_gregs[x + 16]) : (cpu_gregs[x]))
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#define ALTREG(x) ((x) < 8 && (ctx->sr & (SR_MD | SR_RB)) != (SR_MD | SR_RB) \
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#define ALTREG(x) ((x) < 8 && (ctx->flags & (SR_MD | SR_RB)) != (SR_MD | SR_RB)\
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? (cpu_gregs[x + 16]) : (cpu_gregs[x]))
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#define FREG(x) (ctx->fpscr & FPSCR_FR ? (x) ^ 0x10 : (x))
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#define FREG(x) (ctx->flags & FPSCR_FR ? (x) ^ 0x10 : (x))
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#define XHACK(x) ((((x) & 1 ) << 4) | ((x) & 0xe))
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#define XREG(x) (ctx->fpscr & FPSCR_FR ? XHACK(x) ^ 0x10 : XHACK(x))
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#define XREG(x) (ctx->flags & FPSCR_FR ? XHACK(x) ^ 0x10 : XHACK(x))
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#define DREG(x) FREG(x) /* Assumes lsb of (x) is always 0 */
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#define CHECK_NOT_DELAY_SLOT \
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@ -537,7 +535,7 @@ static void _decode_opc(DisasContext * ctx)
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ctx->bstate = BS_STOP;
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return;
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case 0xf3fd: /* fschg */
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tcg_gen_xori_i32(cpu_fpscr, cpu_fpscr, FPSCR_SZ);
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tcg_gen_xori_i32(cpu_fpscr, cpu_fpscr, FPSCR_SZ);
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ctx->bstate = BS_STOP;
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return;
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case 0x0009: /* nop */
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@ -1080,7 +1078,7 @@ static void _decode_opc(DisasContext * ctx)
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return;
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case 0xf00c: /* fmov {F,D,X}Rm,{F,D,X}Rn - FPSCR: Nothing */
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CHECK_FPU_ENABLED
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if (ctx->fpscr & FPSCR_SZ) {
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if (ctx->flags & FPSCR_SZ) {
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TCGv_i64 fp = tcg_temp_new_i64();
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gen_load_fpr64(fp, XREG(B7_4));
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gen_store_fpr64(fp, XREG(B11_8));
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@ -1091,7 +1089,7 @@ static void _decode_opc(DisasContext * ctx)
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return;
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case 0xf00a: /* fmov {F,D,X}Rm,@Rn - FPSCR: Nothing */
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CHECK_FPU_ENABLED
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if (ctx->fpscr & FPSCR_SZ) {
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if (ctx->flags & FPSCR_SZ) {
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TCGv addr_hi = tcg_temp_new();
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int fr = XREG(B7_4);
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tcg_gen_addi_i32(addr_hi, REG(B11_8), 4);
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@ -1104,7 +1102,7 @@ static void _decode_opc(DisasContext * ctx)
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return;
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case 0xf008: /* fmov @Rm,{F,D,X}Rn - FPSCR: Nothing */
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CHECK_FPU_ENABLED
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if (ctx->fpscr & FPSCR_SZ) {
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if (ctx->flags & FPSCR_SZ) {
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TCGv addr_hi = tcg_temp_new();
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int fr = XREG(B11_8);
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tcg_gen_addi_i32(addr_hi, REG(B7_4), 4);
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@ -1117,7 +1115,7 @@ static void _decode_opc(DisasContext * ctx)
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return;
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case 0xf009: /* fmov @Rm+,{F,D,X}Rn - FPSCR: Nothing */
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CHECK_FPU_ENABLED
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if (ctx->fpscr & FPSCR_SZ) {
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if (ctx->flags & FPSCR_SZ) {
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TCGv addr_hi = tcg_temp_new();
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int fr = XREG(B11_8);
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tcg_gen_addi_i32(addr_hi, REG(B7_4), 4);
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@ -1132,7 +1130,7 @@ static void _decode_opc(DisasContext * ctx)
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return;
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case 0xf00b: /* fmov {F,D,X}Rm,@-Rn - FPSCR: Nothing */
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CHECK_FPU_ENABLED
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if (ctx->fpscr & FPSCR_SZ) {
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if (ctx->flags & FPSCR_SZ) {
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TCGv addr = tcg_temp_new_i32();
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int fr = XREG(B7_4);
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tcg_gen_subi_i32(addr, REG(B11_8), 4);
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@ -1155,7 +1153,7 @@ static void _decode_opc(DisasContext * ctx)
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{
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TCGv addr = tcg_temp_new_i32();
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tcg_gen_add_i32(addr, REG(B7_4), REG(0));
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if (ctx->fpscr & FPSCR_SZ) {
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if (ctx->flags & FPSCR_SZ) {
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int fr = XREG(B11_8);
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tcg_gen_qemu_ld32u(cpu_fregs[fr ], addr, ctx->memidx);
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tcg_gen_addi_i32(addr, addr, 4);
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@ -1171,7 +1169,7 @@ static void _decode_opc(DisasContext * ctx)
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{
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TCGv addr = tcg_temp_new();
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tcg_gen_add_i32(addr, REG(B11_8), REG(0));
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if (ctx->fpscr & FPSCR_SZ) {
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if (ctx->flags & FPSCR_SZ) {
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int fr = XREG(B7_4);
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tcg_gen_qemu_ld32u(cpu_fregs[fr ], addr, ctx->memidx);
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tcg_gen_addi_i32(addr, addr, 4);
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@ -1190,7 +1188,7 @@ static void _decode_opc(DisasContext * ctx)
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case 0xf005: /* fcmp/gt Rm,Rn - FPSCR: R[PR,Enable.V]/W[Cause,Flag] */
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{
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CHECK_FPU_ENABLED
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if (ctx->fpscr & FPSCR_PR) {
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if (ctx->flags & FPSCR_PR) {
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TCGv_i64 fp0, fp1;
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if (ctx->opcode & 0x0110)
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@ -1259,7 +1257,7 @@ static void _decode_opc(DisasContext * ctx)
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case 0xf00e: /* fmac FR0,RM,Rn */
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{
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CHECK_FPU_ENABLED
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if (ctx->fpscr & FPSCR_PR) {
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if (ctx->flags & FPSCR_PR) {
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break; /* illegal instruction */
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} else {
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gen_helper_fmac_FT(cpu_fregs[FREG(B11_8)], cpu_env,
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@ -1789,7 +1787,7 @@ static void _decode_opc(DisasContext * ctx)
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return;
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case 0xf02d: /* float FPUL,FRn/DRn - FPSCR: R[PR,Enable.I]/W[Cause,Flag] */
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CHECK_FPU_ENABLED
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if (ctx->fpscr & FPSCR_PR) {
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if (ctx->flags & FPSCR_PR) {
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TCGv_i64 fp;
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if (ctx->opcode & 0x0100)
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break; /* illegal instruction */
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@ -1804,7 +1802,7 @@ static void _decode_opc(DisasContext * ctx)
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return;
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case 0xf03d: /* ftrc FRm/DRm,FPUL - FPSCR: R[PR,Enable.V]/W[Cause,Flag] */
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CHECK_FPU_ENABLED
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if (ctx->fpscr & FPSCR_PR) {
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if (ctx->flags & FPSCR_PR) {
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TCGv_i64 fp;
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if (ctx->opcode & 0x0100)
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break; /* illegal instruction */
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@ -1825,7 +1823,7 @@ static void _decode_opc(DisasContext * ctx)
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return;
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case 0xf05d: /* fabs FRn/DRn */
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CHECK_FPU_ENABLED
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if (ctx->fpscr & FPSCR_PR) {
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if (ctx->flags & FPSCR_PR) {
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if (ctx->opcode & 0x0100)
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break; /* illegal instruction */
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TCGv_i64 fp = tcg_temp_new_i64();
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@ -1839,7 +1837,7 @@ static void _decode_opc(DisasContext * ctx)
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return;
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case 0xf06d: /* fsqrt FRn */
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CHECK_FPU_ENABLED
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if (ctx->fpscr & FPSCR_PR) {
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if (ctx->flags & FPSCR_PR) {
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if (ctx->opcode & 0x0100)
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break; /* illegal instruction */
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TCGv_i64 fp = tcg_temp_new_i64();
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@ -1857,13 +1855,13 @@ static void _decode_opc(DisasContext * ctx)
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break;
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case 0xf08d: /* fldi0 FRn - FPSCR: R[PR] */
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CHECK_FPU_ENABLED
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if (!(ctx->fpscr & FPSCR_PR)) {
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if (!(ctx->flags & FPSCR_PR)) {
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tcg_gen_movi_i32(cpu_fregs[FREG(B11_8)], 0);
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}
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return;
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case 0xf09d: /* fldi1 FRn - FPSCR: R[PR] */
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CHECK_FPU_ENABLED
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if (!(ctx->fpscr & FPSCR_PR)) {
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if (!(ctx->flags & FPSCR_PR)) {
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tcg_gen_movi_i32(cpu_fregs[FREG(B11_8)], 0x3f800000);
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}
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return;
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@ -1887,7 +1885,7 @@ static void _decode_opc(DisasContext * ctx)
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return;
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case 0xf0ed: /* fipr FVm,FVn */
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CHECK_FPU_ENABLED
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if ((ctx->fpscr & FPSCR_PR) == 0) {
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if ((ctx->flags & FPSCR_PR) == 0) {
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TCGv m, n;
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m = tcg_const_i32((ctx->opcode >> 8) & 3);
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n = tcg_const_i32((ctx->opcode >> 10) & 3);
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@ -1900,7 +1898,7 @@ static void _decode_opc(DisasContext * ctx)
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case 0xf0fd: /* ftrv XMTRX,FVn */
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CHECK_FPU_ENABLED
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if ((ctx->opcode & 0x0300) == 0x0100 &&
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(ctx->fpscr & FPSCR_PR) == 0) {
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(ctx->flags & FPSCR_PR) == 0) {
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TCGv n;
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n = tcg_const_i32((ctx->opcode >> 10) & 3);
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gen_helper_ftrv(cpu_env, n);
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@ -1974,16 +1972,14 @@ gen_intermediate_code_internal(CPUSH4State * env, TranslationBlock * tb,
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ctx.pc = pc_start;
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ctx.flags = (uint32_t)tb->flags;
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ctx.bstate = BS_NONE;
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ctx.sr = env->sr;
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ctx.fpscr = env->fpscr;
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ctx.memidx = (env->sr & SR_MD) == 0 ? 1 : 0;
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ctx.memidx = (ctx.flags & SR_MD) == 0 ? 1 : 0;
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/* We don't know if the delayed pc came from a dynamic or static branch,
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so assume it is a dynamic branch. */
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ctx.delayed_pc = -1; /* use delayed pc from env pointer */
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ctx.tb = tb;
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ctx.singlestep_enabled = env->singlestep_enabled;
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ctx.features = env->features;
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ctx.has_movcal = (tb->flags & TB_FLAG_PENDING_MOVCA);
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ctx.has_movcal = (ctx.flags & TB_FLAG_PENDING_MOVCA);
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ii = -1;
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num_insns = 0;
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