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trivial patches for 2015-03-19

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Merge remote-tracking branch 'remotes/mjt/tags/pull-trivial-patches-2015-03-19' into staging

trivial patches for 2015-03-19

# gpg: Signature made Thu Mar 19 08:57:54 2015 GMT using RSA key ID A4C3D7DB
# gpg: Good signature from "Michael Tokarev <mjt@tls.msk.ru>"
# gpg:                 aka "Michael Tokarev <mjt@corpit.ru>"
# gpg:                 aka "Michael Tokarev <mjt@debian.org>"

* remotes/mjt/tags/pull-trivial-patches-2015-03-19: (24 commits)
  qga/commands-posix: Fix resource leak
  elf-loader: Add missing error handling for call of lseek
  elf-loader: Fix truncation warning from coverity
  hmp: Fix texinfo documentation
  Fix typos in comments
  qtest/ahci: Fix a bit mask expression
  vl: fix resource leak with monitor_fdset_add_fd
  smbios: add max speed comdline option for type-17 (meory device) structure
  pc-dimm: Add description for device list.
  configure: enable kvm on x32
  error: Replace error_report() & error_free() with error_report_err()
  arm: fix memory leak
  qmp: Drop unused .user_print from command definitions
  hmp: Fix definition of command quit
  target-moxie: Fix warnings from Sparse (one-bit signed bitfield)
  block/qapi: Fix Sparse warning
  Fix remaining warnings from Sparse (void return)
  qom: Fix warning from Sparse
  target-mips: Fix warning from Sparse
  arm/nseries: Fix warnings from Sparse
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2015-03-19 14:10:20 +00:00
commit 7a9a5e72e8
52 changed files with 191 additions and 161 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
backends/tpm.c
View File

@ -36,7 +36,7 @@ void tpm_backend_destroy(TPMBackend *s)
{
TPMBackendClass *k = TPM_BACKEND_GET_CLASS(s);
return k->ops->destroy(s);
k->ops->destroy(s);
}
int tpm_backend_init(TPMBackend *s, TPMState *state,

2
block/qapi.c
View File

@ -414,7 +414,7 @@ BlockStatsList *qmp_query_blockstats(bool has_query_nodes,
static char *get_human_readable_size(char *buf, int buf_size, int64_t size)
{
static const char suffixes[NB_SUFFIXES] = "KMGT";
static const char suffixes[NB_SUFFIXES] = {'K', 'M', 'G', 'T'};
int64_t base;
int i;

4
configure vendored
View File

@ -5268,7 +5268,9 @@ case "$target_name" in
\( "$target_name" = "ppcemb" -a "$cpu" = "ppc64" \) -o \
\( "$target_name" = "mipsel" -a "$cpu" = "mips" \) -o \
\( "$target_name" = "x86_64" -a "$cpu" = "i386" \) -o \
\( "$target_name" = "i386" -a "$cpu" = "x86_64" \) \) ; then
\( "$target_name" = "i386" -a "$cpu" = "x86_64" \) -o \
\( "$target_name" = "x86_64" -a "$cpu" = "x32" \) -o \
\( "$target_name" = "i386" -a "$cpu" = "x32" \) \) ; then
echo "CONFIG_KVM=y" >> $config_target_mak
if test "$vhost_net" = "yes" ; then
echo "CONFIG_VHOST_NET=y" >> $config_target_mak

13
disas/cris.c
View File

@ -1210,21 +1210,10 @@ cris_cc_strings[] =
"le",
"a",
/* This is a placeholder. In v0, this would be "ext". In v32, this
is "sb". See cris_conds15. */
is "sb". */
"wf"
};
/* Different names and semantics for condition 1111 (0xf). */
const struct cris_cond15 cris_cond15s[] =
{
/* FIXME: In what version did condition "ext" disappear? */
{"ext", cris_ver_v0_3},
{"wf", cris_ver_v10},
{"sb", cris_ver_v32p},
{NULL, 0}
};
/*
* Local variables:
* eval: (c-set-style "gnu")

2
fsdev/virtfs-proxy-helper.c
View File

@ -117,7 +117,7 @@ error:
static int init_capabilities(void)
{
/* helper needs following capbabilities only */
/* helper needs following capabilities only */
cap_value_t cap_list[] = {
CAP_CHOWN,
CAP_DAC_OVERRIDE,

42
hmp-commands.hx
View File

@ -47,7 +47,6 @@ ETEXI
.args_type = "",
.params = "",
.help = "quit the emulator",
.user_print = monitor_user_noop,
.mhandler.cmd = hmp_quit,
},
@ -205,7 +204,6 @@ ETEXI
STEXI
@item change @var{device} @var{setting}
@findex change
Change the configuration of a device.
@table @option
@ -523,7 +521,6 @@ ETEXI
STEXI
@item p or print/@var{fmt} @var{expr}
@findex print
Print expression value. Only the @var{format} part of @var{fmt} is
used.
ETEXI
@ -537,6 +534,8 @@ ETEXI
},
STEXI
@item i/@var{fmt} @var{addr} [.@var{index}]
@findex i
Read I/O port.
ETEXI
@ -549,6 +548,8 @@ ETEXI
},
STEXI
@item o/@var{fmt} @var{addr} @var{val}
@findex o
Write to I/O port.
ETEXI
@ -564,7 +565,6 @@ ETEXI
STEXI
@item sendkey @var{keys}
@findex sendkey
Send @var{keys} to the guest. @var{keys} could be the name of the
key or the raw value in hexadecimal format. Use @code{-} to press
several keys simultaneously. Example:
@ -587,7 +587,6 @@ ETEXI
STEXI
@item system_reset
@findex system_reset
Reset the system.
ETEXI
@ -602,7 +601,6 @@ ETEXI
STEXI
@item system_powerdown
@findex system_powerdown
Power down the system (if supported).
ETEXI
@ -617,7 +615,6 @@ ETEXI
STEXI
@item sum @var{addr} @var{size}
@findex sum
Compute the checksum of a memory region.
ETEXI
@ -632,7 +629,6 @@ ETEXI
STEXI
@item usb_add @var{devname}
@findex usb_add
Add the USB device @var{devname}. For details of available devices see
@ref{usb_devices}
ETEXI
@ -648,7 +644,6 @@ ETEXI
STEXI
@item usb_del @var{devname}
@findex usb_del
Remove the USB device @var{devname} from the QEMU virtual USB
hub. @var{devname} has the syntax @code{bus.addr}. Use the monitor
command @code{info usb} to see the devices you can remove.
@ -667,7 +662,6 @@ ETEXI
STEXI
@item device_add @var{config}
@findex device_add
Add device.
ETEXI
@ -683,7 +677,6 @@ ETEXI
STEXI
@item device_del @var{id}
@findex device_del
Remove device @var{id}.
ETEXI
@ -824,7 +817,6 @@ ETEXI
STEXI
@item boot_set @var{bootdevicelist}
@findex boot_set
Define new values for the boot device list. Those values will override
the values specified on the command line through the @code{-boot} option.
@ -1539,9 +1531,9 @@ ETEXI
},
STEXI
@item block_set_io_throttle @var{device} @var{bps} @var{bps_rd} @var{bps_wr} @var{iops} @var{iops_rd} @var{iops_wr}
@findex block_set_io_throttle
Change I/O throttle limits for a block drive to @var{bps} @var{bps_rd} @var{bps_wr} @var{iops} @var{iops_rd} @var{iops_wr}
@item block_passwd @var{device} @var{password}
@findex block_passwd
Set the encrypted device @var{device} password to @var{password}
ETEXI
{
@ -1553,9 +1545,9 @@ ETEXI
},
STEXI
@item block_passwd @var{device} @var{password}
@findex block_passwd
Set the encrypted device @var{device} password to @var{password}
@item block_set_io_throttle @var{device} @var{bps} @var{bps_rd} @var{bps_wr} @var{iops} @var{iops_rd} @var{iops_wr}
@findex block_set_io_throttle
Change I/O throttle limits for a block drive to @var{bps} @var{bps_rd} @var{bps_wr} @var{iops} @var{iops_rd} @var{iops_wr}
ETEXI
{
@ -1569,7 +1561,6 @@ ETEXI
STEXI
@item set_password [ vnc | spice ] password [ action-if-connected ]
@findex set_password
Change spice/vnc password. Use zero to make the password stay valid
forever. @var{action-if-connected} specifies what should happen in
case a connection is established: @var{fail} makes the password change
@ -1589,7 +1580,6 @@ ETEXI
STEXI
@item expire_password [ vnc | spice ] expire-time
@findex expire_password
Specify when a password for spice/vnc becomes
invalid. @var{expire-time} accepts:
@ -1620,9 +1610,8 @@ ETEXI
},
STEXI
@item chardev_add args
@findex chardev_add
@item chardev-add args
@findex chardev-add
chardev_add accepts the same parameters as the -chardev command line switch.
ETEXI
@ -1637,9 +1626,8 @@ ETEXI
},
STEXI
@item chardev_remove id
@findex chardev_remove
@item chardev-remove id
@findex chardev-remove
Removes the chardev @var{id}.
ETEXI
@ -1655,7 +1643,6 @@ ETEXI
STEXI
@item qemu-io @var{device} @var{command}
@findex qemu-io
Executes a qemu-io command on the given block device.
ETEXI
@ -1670,6 +1657,7 @@ ETEXI
STEXI
@item cpu-add @var{id}
@findex cpu-add
Add CPU with id @var{id}
ETEXI

4
hw/9pfs/virtio-9p-handle.c
View File

@ -140,7 +140,7 @@ static int handle_opendir(FsContext *ctx,
static void handle_rewinddir(FsContext *ctx, V9fsFidOpenState *fs)
{
return rewinddir(fs->dir);
rewinddir(fs->dir);
}
static off_t handle_telldir(FsContext *ctx, V9fsFidOpenState *fs)
@ -157,7 +157,7 @@ static int handle_readdir_r(FsContext *ctx, V9fsFidOpenState *fs,
static void handle_seekdir(FsContext *ctx, V9fsFidOpenState *fs, off_t off)
{
return seekdir(fs->dir, off);
seekdir(fs->dir, off);
}
static ssize_t handle_preadv(FsContext *ctx, V9fsFidOpenState *fs,

4
hw/9pfs/virtio-9p-local.c
View File

@ -378,7 +378,7 @@ static int local_opendir(FsContext *ctx,
static void local_rewinddir(FsContext *ctx, V9fsFidOpenState *fs)
{
return rewinddir(fs->dir);
rewinddir(fs->dir);
}
static off_t local_telldir(FsContext *ctx, V9fsFidOpenState *fs)
@ -409,7 +409,7 @@ again:
static void local_seekdir(FsContext *ctx, V9fsFidOpenState *fs, off_t off)
{
return seekdir(fs->dir, off);
seekdir(fs->dir, off);
}
static ssize_t local_preadv(FsContext *ctx, V9fsFidOpenState *fs,

4
hw/9pfs/virtio-9p-proxy.c
View File

@ -669,7 +669,7 @@ static int proxy_opendir(FsContext *ctx,
static void proxy_rewinddir(FsContext *ctx, V9fsFidOpenState *fs)
{
return rewinddir(fs->dir);
rewinddir(fs->dir);
}
static off_t proxy_telldir(FsContext *ctx, V9fsFidOpenState *fs)
@ -686,7 +686,7 @@ static int proxy_readdir_r(FsContext *ctx, V9fsFidOpenState *fs,
static void proxy_seekdir(FsContext *ctx, V9fsFidOpenState *fs, off_t off)
{
return seekdir(fs->dir, off);
seekdir(fs->dir, off);
}
static ssize_t proxy_preadv(FsContext *ctx, V9fsFidOpenState *fs,

3
hw/9pfs/virtio-9p.c
View File

@ -1950,7 +1950,8 @@ static void v9fs_write(void *opaque)
err = pdu_unmarshal(pdu, offset, "dqd", &fid, &off, &count);
if (err < 0) {
return complete_pdu(s, pdu, err);
complete_pdu(s, pdu, err);
return;
}
offset += err;
v9fs_init_qiov_from_pdu(&qiov_full, pdu, offset, count, true);

1
hw/arm/digic_boards.c
View File

@ -113,6 +113,7 @@ static void digic_load_rom(DigicBoardState *s, hwaddr addr,
error_report("Couldn't load rom image '%s'.", filename);
exit(1);
}
g_free(fn);
}
}

1
hw/arm/highbank.c
View File

@ -282,6 +282,7 @@ static void calxeda_init(MachineState *machine, enum cxmachines machine_id)
if (load_image_targphys("sysram.bin", 0xfff88000, filesize) < 0) {
hw_error("Unable to load %s\n", bios_name);
}
g_free(sysboot_filename);
} else {
hw_error("Unable to find %s\n", bios_name);
}

4
hw/arm/nseries.c
View File

@ -1403,12 +1403,12 @@ static struct arm_boot_info n810_binfo = {
static void n800_init(MachineState *machine)
{
return n8x0_init(machine, &n800_binfo, 800);
n8x0_init(machine, &n800_binfo, 800);
}
static void n810_init(MachineState *machine)
{
return n8x0_init(machine, &n810_binfo, 810);
n8x0_init(machine, &n810_binfo, 810);
}
static QEMUMachine n800_machine = {

65
hw/arm/omap1.c
View File

@ -207,7 +207,8 @@ static void omap_mpu_timer_write(void *opaque, hwaddr addr,
struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) opaque;
if (size != 4) {
return omap_badwidth_write32(opaque, addr, value);
omap_badwidth_write32(opaque, addr, value);
return;
}
switch (addr) {
@ -314,7 +315,8 @@ static void omap_wd_timer_write(void *opaque, hwaddr addr,
struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) opaque;
if (size != 2) {
return omap_badwidth_write16(opaque, addr, value);
omap_badwidth_write16(opaque, addr, value);
return;
}
switch (addr) {
@ -440,7 +442,8 @@ static void omap_os_timer_write(void *opaque, hwaddr addr,
int offset = addr & OMAP_MPUI_REG_MASK;
if (size != 4) {
return omap_badwidth_write32(opaque, addr, value);
omap_badwidth_write32(opaque, addr, value);
return;
}
switch (offset) {
@ -585,7 +588,8 @@ static void omap_ulpd_pm_write(void *opaque, hwaddr addr,
uint16_t diff;
if (size != 2) {
return omap_badwidth_write16(opaque, addr, value);
omap_badwidth_write16(opaque, addr, value);
return;
}
switch (addr) {
@ -857,7 +861,8 @@ static void omap_pin_cfg_write(void *opaque, hwaddr addr,
uint32_t diff;
if (size != 4) {
return omap_badwidth_write32(opaque, addr, value);
omap_badwidth_write32(opaque, addr, value);
return;
}
switch (addr) {
@ -1012,7 +1017,8 @@ static void omap_id_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
if (size != 4) {
return omap_badwidth_write32(opaque, addr, value);
omap_badwidth_write32(opaque, addr, value);
return;
}
OMAP_BAD_REG(addr);
@ -1081,7 +1087,8 @@ static void omap_mpui_write(void *opaque, hwaddr addr,
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
if (size != 4) {
return omap_badwidth_write32(opaque, addr, value);
omap_badwidth_write32(opaque, addr, value);
return;
}
switch (addr) {
@ -1175,7 +1182,8 @@ static void omap_tipb_bridge_write(void *opaque, hwaddr addr,
struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) opaque;
if (size < 2) {
return omap_badwidth_write16(opaque, addr, value);
omap_badwidth_write16(opaque, addr, value);
return;
}
switch (addr) {
@ -1284,7 +1292,8 @@ static void omap_tcmi_write(void *opaque, hwaddr addr,
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
if (size != 4) {
return omap_badwidth_write32(opaque, addr, value);
omap_badwidth_write32(opaque, addr, value);
return;
}
switch (addr) {
@ -1379,7 +1388,8 @@ static void omap_dpll_write(void *opaque, hwaddr addr,
int div, mult;
if (size != 2) {
return omap_badwidth_write16(opaque, addr, value);
omap_badwidth_write16(opaque, addr, value);
return;
}
if (addr == 0x00) { /* CTL_REG */
@ -1647,7 +1657,8 @@ static void omap_clkm_write(void *opaque, hwaddr addr,
};
if (size != 2) {
return omap_badwidth_write16(opaque, addr, value);
omap_badwidth_write16(opaque, addr, value);
return;
}
switch (addr) {
@ -1775,7 +1786,8 @@ static void omap_clkdsp_write(void *opaque, hwaddr addr,
uint16_t diff;
if (size != 2) {
return omap_badwidth_write16(opaque, addr, value);
omap_badwidth_write16(opaque, addr, value);
return;
}
switch (addr) {
@ -1982,7 +1994,8 @@ static void omap_mpuio_write(void *opaque, hwaddr addr,
int ln;
if (size != 2) {
return omap_badwidth_write16(opaque, addr, value);
omap_badwidth_write16(opaque, addr, value);
return;
}
switch (offset) {
@ -2210,7 +2223,8 @@ static void omap_uwire_write(void *opaque, hwaddr addr,
int offset = addr & OMAP_MPUI_REG_MASK;
if (size != 2) {
return omap_badwidth_write16(opaque, addr, value);
omap_badwidth_write16(opaque, addr, value);
return;
}
switch (offset) {
@ -2349,7 +2363,8 @@ static void omap_pwl_write(void *opaque, hwaddr addr,
int offset = addr & OMAP_MPUI_REG_MASK;
if (size != 1) {
return omap_badwidth_write8(opaque, addr, value);
omap_badwidth_write8(opaque, addr, value);
return;
}
switch (offset) {
@ -2444,7 +2459,8 @@ static void omap_pwt_write(void *opaque, hwaddr addr,
int offset = addr & OMAP_MPUI_REG_MASK;
if (size != 1) {
return omap_badwidth_write8(opaque, addr, value);
omap_badwidth_write8(opaque, addr, value);
return;
}
switch (offset) {
@ -2637,7 +2653,8 @@ static void omap_rtc_write(void *opaque, hwaddr addr,
time_t ti[2];
if (size != 1) {
return omap_badwidth_write8(opaque, addr, value);
omap_badwidth_write8(opaque, addr, value);
return;
}
switch (offset) {
@ -3410,9 +3427,14 @@ static void omap_mcbsp_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
switch (size) {
case 2: return omap_mcbsp_writeh(opaque, addr, value);
case 4: return omap_mcbsp_writew(opaque, addr, value);
default: return omap_badwidth_write16(opaque, addr, value);
case 2:
omap_mcbsp_writeh(opaque, addr, value);
break;
case 4:
omap_mcbsp_writew(opaque, addr, value);
break;
default:
omap_badwidth_write16(opaque, addr, value);
}
}
@ -3586,7 +3608,8 @@ static void omap_lpg_write(void *opaque, hwaddr addr,
int offset = addr & OMAP_MPUI_REG_MASK;
if (size != 1) {
return omap_badwidth_write8(opaque, addr, value);
omap_badwidth_write8(opaque, addr, value);
return;
}
switch (offset) {

12
hw/arm/omap2.c
View File

@ -447,7 +447,8 @@ static void omap_eac_write(void *opaque, hwaddr addr,
struct omap_eac_s *s = (struct omap_eac_s *) opaque;
if (size != 2) {
return omap_badwidth_write16(opaque, addr, value);
omap_badwidth_write16(opaque, addr, value);
return;
}
switch (addr) {
@ -692,7 +693,8 @@ static void omap_sti_write(void *opaque, hwaddr addr,
struct omap_sti_s *s = (struct omap_sti_s *) opaque;
if (size != 4) {
return omap_badwidth_write32(opaque, addr, value);
omap_badwidth_write32(opaque, addr, value);
return;
}
switch (addr) {
@ -757,7 +759,8 @@ static void omap_sti_fifo_write(void *opaque, hwaddr addr,
uint8_t byte = value;
if (size != 1) {
return omap_badwidth_write8(opaque, addr, size);
omap_badwidth_write8(opaque, addr, size);
return;
}
if (ch == STI_TRACE_CONTROL_CHANNEL) {
@ -1359,7 +1362,8 @@ static void omap_prcm_write(void *opaque, hwaddr addr,
struct omap_prcm_s *s = (struct omap_prcm_s *) opaque;
if (size != 4) {
return omap_badwidth_write32(opaque, addr, value);
omap_badwidth_write32(opaque, addr, value);
return;
}
switch (addr) {

3
hw/arm/vexpress.c
View File

@ -562,7 +562,7 @@ static void vexpress_common_init(MachineState *machine)
* If a bios file was provided, attempt to map it into memory
*/
if (bios_name) {
const char *fn;
char *fn;
if (drive_get(IF_PFLASH, 0, 0)) {
error_report("The contents of the first flash device may be "
@ -576,6 +576,7 @@ static void vexpress_common_init(MachineState *machine)
error_report("Could not load ROM image '%s'", bios_name);
exit(1);
}
g_free(fn);
}
/* Motherboard peripherals: the wiring is the same but the

5
hw/arm/virt.c
View File

@ -552,7 +552,7 @@ static void create_flash(const VirtBoardInfo *vbi)
char *nodename;
if (bios_name) {
const char *fn;
char *fn;
if (drive_get(IF_PFLASH, 0, 0)) {
error_report("The contents of the first flash device may be "
@ -565,6 +565,7 @@ static void create_flash(const VirtBoardInfo *vbi)
error_report("Could not load ROM image '%s'", bios_name);
exit(1);
}
g_free(fn);
}
create_one_flash("virt.flash0", flashbase, flashsize);
@ -770,7 +771,7 @@ static void machvirt_init(MachineState *machine)
cc->parse_features(CPU(cpuobj), cpuopts, &err);
g_free(cpuopts);
if (err) {
error_report("%s", error_get_pretty(err));
error_report_err(err);
exit(1);
}

3
hw/char/omap_uart.c
View File

@ -112,7 +112,8 @@ static void omap_uart_write(void *opaque, hwaddr addr,
struct omap_uart_s *s = (struct omap_uart_s *) opaque;
if (size == 4) {
return omap_badwidth_write8(opaque, addr, value);
omap_badwidth_write8(opaque, addr, value);
return;
}
switch (addr) {

2
hw/core/loader.c
View File

@ -267,7 +267,7 @@ int load_aout(const char *filename, hwaddr addr, int max_sz,
/* ELF loader */
static void *load_at(int fd, int offset, int size)
static void *load_at(int fd, off_t offset, size_t size)
{
void *ptr;
if (lseek(fd, offset, SEEK_SET) < 0)

15
hw/display/omap_dss.c
View File

@ -212,7 +212,8 @@ static void omap_diss_write(void *opaque, hwaddr addr,
struct omap_dss_s *s = (struct omap_dss_s *) opaque;
if (size != 4) {
return omap_badwidth_write32(opaque, addr, value);
omap_badwidth_write32(opaque, addr, value);
return;
}
switch (addr) {
@ -377,7 +378,8 @@ static void omap_disc_write(void *opaque, hwaddr addr,
struct omap_dss_s *s = (struct omap_dss_s *) opaque;
if (size != 4) {
return omap_badwidth_write32(opaque, addr, value);
omap_badwidth_write32(opaque, addr, value);
return;
}
switch (addr) {
@ -736,7 +738,8 @@ static void omap_rfbi_write(void *opaque, hwaddr addr,
struct omap_dss_s *s = (struct omap_dss_s *) opaque;
if (size != 4) {
return omap_badwidth_write32(opaque, addr, value);
omap_badwidth_write32(opaque, addr, value);
return;
}
switch (addr) {
@ -928,7 +931,8 @@ static void omap_venc_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
if (size != 4) {
return omap_badwidth_write32(opaque, addr, size);
omap_badwidth_write32(opaque, addr, size);
return;
}
switch (addr) {
@ -1016,7 +1020,8 @@ static void omap_im3_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
if (size != 4) {
return omap_badwidth_write32(opaque, addr, value);
omap_badwidth_write32(opaque, addr, value);
return;
}
switch (addr) {

2
hw/display/vga.c
View File

@ -1997,7 +1997,7 @@ static void vga_mem_write(void *opaque, hwaddr addr,
{
VGACommonState *s = opaque;
return vga_mem_writeb(s, addr, data);
vga_mem_writeb(s, addr, data);
}
const MemoryRegionOps vga_mem_ops = {

8
hw/dma/omap_dma.c
View File

@ -136,7 +136,7 @@ struct omap_dma_s {
static inline void omap_dma_interrupts_update(struct omap_dma_s *s)
{
return s->intr_update(s);
s->intr_update(s);
}
static void omap_dma_channel_load(struct omap_dma_channel_s *ch)
@ -1502,7 +1502,8 @@ static void omap_dma_write(void *opaque, hwaddr addr,
int reg, ch;
if (size != 2) {
return omap_badwidth_write16(opaque, addr, value);
omap_badwidth_write16(opaque, addr, value);
return;
}
switch (addr) {
@ -1857,7 +1858,8 @@ static void omap_dma4_write(void *opaque, hwaddr addr,
struct omap_dma_channel_s *ch;
if (size == 1) {
return omap_badwidth_write16(opaque, addr, value);
omap_badwidth_write16(opaque, addr, value);
return;
}
switch (addr) {

3
hw/gpio/omap_gpio.c
View File

@ -113,7 +113,8 @@ static void omap_gpio_write(void *opaque, hwaddr addr,
int ln;
if (size != 2) {
return omap_badwidth_write16(opaque, addr, value);
omap_badwidth_write16(opaque, addr, value);
return;
}
switch (offset) {

10
hw/i386/smbios.c
View File

@ -91,6 +91,7 @@ static struct {
static struct {
const char *loc_pfx, *bank, *manufacturer, *serial, *asset, *part;
uint16_t speed;
} type17;
static QemuOptsList qemu_smbios_opts = {
@ -304,6 +305,10 @@ static const QemuOptDesc qemu_smbios_type17_opts[] = {
.name = "part",
.type = QEMU_OPT_STRING,
.help = "part number",
},{
.name = "speed",
.type = QEMU_OPT_NUMBER,
.help = "maximum capable speed",
},
{ /* end of list */ }
};
@ -697,13 +702,13 @@ static void smbios_build_type_17_table(unsigned instance, uint64_t size)
SMBIOS_TABLE_SET_STR(17, bank_locator_str, type17.bank);
t->memory_type = 0x07; /* RAM */
t->type_detail = cpu_to_le16(0x02); /* Other */
t->speed = cpu_to_le16(0); /* Unknown */
t->speed = cpu_to_le16(type17.speed);
SMBIOS_TABLE_SET_STR(17, manufacturer_str, type17.manufacturer);
SMBIOS_TABLE_SET_STR(17, serial_number_str, type17.serial);
SMBIOS_TABLE_SET_STR(17, asset_tag_number_str, type17.asset);
SMBIOS_TABLE_SET_STR(17, part_number_str, type17.part);
t->attributes = 0; /* Unknown */
t->configured_clock_speed = cpu_to_le16(0); /* Unknown */
t->configured_clock_speed = t->speed; /* reuse value for max speed */
t->minimum_voltage = cpu_to_le16(0); /* Unknown */
t->maximum_voltage = cpu_to_le16(0); /* Unknown */
t->configured_voltage = cpu_to_le16(0); /* Unknown */
@ -1083,6 +1088,7 @@ void smbios_entry_add(QemuOpts *opts)
save_opt(&type17.serial, opts, "serial");
save_opt(&type17.asset, opts, "asset");
save_opt(&type17.part, opts, "part");
type17.speed = qemu_opt_get_number(opts, "speed", 0);
return;
default:
error_report("Don't know how to build fields for SMBIOS type %ld",

3
hw/intc/arm_gic.c
View File

@ -704,7 +704,8 @@ static void gic_cpu_write(GICState *s, int cpu, int offset, uint32_t value)
s->bpr[cpu] = (value & 0x7);
break;
case 0x10: /* End Of Interrupt */
return gic_complete_irq(s, cpu, value & 0x3ff);
gic_complete_irq(s, cpu, value & 0x3ff);
return;
case 0x1c: /* Aliased Binary Point */
if (s->revision >= 2) {
s->abpr[cpu] = (value & 0x7);

8
hw/intc/etraxfs_pic.c
View File

@ -131,11 +131,13 @@ static void nmi_handler(void *opaque, int irq, int level)
}
static void irq_handler(void *opaque, int irq, int level)
{
{
struct etrax_pic *fs = (void *)opaque;
if (irq >= 30)
return nmi_handler(opaque, irq, level);
if (irq >= 30) {
nmi_handler(opaque, irq, level);
return;
}
irq -= 1;
fs->regs[R_R_VECT] &= ~(1 << irq);

1
hw/mem/pc-dimm.c
View File

@ -351,6 +351,7 @@ static void pc_dimm_class_init(ObjectClass *oc, void *data)
dc->realize = pc_dimm_realize;
dc->props = pc_dimm_properties;
dc->desc = "DIMM memory module";
ddc->get_memory_region = pc_dimm_get_memory_region;
}

3
hw/misc/omap_gpmc.c
View File

@ -624,7 +624,8 @@ static void omap_gpmc_write(void *opaque, hwaddr addr,
struct omap_gpmc_cs_file_s *f;
if (size != 4 && gpmc_wordaccess_only(addr)) {
return omap_badwidth_write32(opaque, addr, value);
omap_badwidth_write32(opaque, addr, value);
return;
}
switch (addr) {

3
hw/misc/omap_l4.c
View File

@ -82,7 +82,8 @@ static void omap_l4ta_write(void *opaque, hwaddr addr,
struct omap_target_agent_s *s = (struct omap_target_agent_s *) opaque;
if (size != 4) {
return omap_badwidth_write32(opaque, addr, value);
omap_badwidth_write32(opaque, addr, value);
return;
}
switch (addr) {

3
hw/misc/omap_sdrc.c
View File

@ -92,7 +92,8 @@ static void omap_sdrc_write(void *opaque, hwaddr addr,
struct omap_sdrc_s *s = (struct omap_sdrc_s *) opaque;
if (size != 4) {
return omap_badwidth_write32(opaque, addr, value);
omap_badwidth_write32(opaque, addr, value);
return;
}
switch (addr) {

3
hw/misc/omap_tap.c
View File

@ -95,7 +95,8 @@ static void omap_tap_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
if (size != 4) {
return omap_badwidth_write32(opaque, addr, value);
omap_badwidth_write32(opaque, addr, value);
return;
}
OMAP_BAD_REG(addr);

2
hw/nvram/fw_cfg.c
View File

@ -472,7 +472,7 @@ void fw_cfg_add_string(FWCfgState *s, uint16_t key, const char *value)
{
size_t sz = strlen(value) + 1;
return fw_cfg_add_bytes(s, key, g_memdup(value, sz), sz);
fw_cfg_add_bytes(s, key, g_memdup(value, sz), sz);
}
void fw_cfg_add_i16(FWCfgState *s, uint16_t key, uint16_t value)

3
hw/sd/omap_mmc.c
View File

@ -406,7 +406,8 @@ static void omap_mmc_write(void *opaque, hwaddr offset,
struct omap_mmc_s *s = (struct omap_mmc_s *) opaque;
if (size != 2) {
return omap_badwidth_write16(opaque, offset, value);
omap_badwidth_write16(opaque, offset, value);
return;
}
switch (offset) {

3
hw/ssi/omap_spi.c
View File

@ -226,7 +226,8 @@ static void omap_mcspi_write(void *opaque, hwaddr addr,
int ch = 0;
if (size != 4) {
return omap_badwidth_write32(opaque, addr, value);
omap_badwidth_write32(opaque, addr, value);
return;
}
switch (addr) {

2
hw/timer/a9gtimer.c
View File

@ -121,7 +121,7 @@ static void a9_gtimer_update_no_sync(void *opaque)
{
A9GTimerState *s = A9_GTIMER(opaque);
return a9_gtimer_update(s, false);
a9_gtimer_update(s, false);
}
static uint64_t a9_gtimer_read(void *opaque, hwaddr addr, unsigned size)

2
hw/timer/omap_gptimer.c
View File

@ -444,7 +444,7 @@ static void omap_gp_timer_writeh(void *opaque, hwaddr addr,
struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque;
if (addr & 2)
return omap_gp_timer_write(opaque, addr, (value << 16) | s->writeh);
omap_gp_timer_write(opaque, addr, (value << 16) | s->writeh);
else
s->writeh = (uint16_t) value;
}

2
hw/tpm/tpm_tis.c
View File

@ -868,7 +868,7 @@ static void tpm_tis_mmio_write_intern(void *opaque, hwaddr addr,
static void tpm_tis_mmio_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
return tpm_tis_mmio_write_intern(opaque, addr, val, size, false);
tpm_tis_mmio_write_intern(opaque, addr, val, size, false);
}
static const MemoryRegionOps tpm_tis_memory_ops = {

20
hw/usb/hcd-musb.c
View File

@ -554,8 +554,10 @@ static void musb_schedule_cb(USBPort *port, USBPacket *packey)
timeout = ep->timeout[dir];
else if (ep->interrupt[dir])
timeout = 8;
else
return musb_cb_tick(ep);
else {
musb_cb_tick(ep);
return;
}
if (!ep->intv_timer[dir])
ep->intv_timer[dir] = timer_new_ns(QEMU_CLOCK_VIRTUAL, musb_cb_tick, ep);
@ -772,9 +774,11 @@ static void musb_rx_packet_complete(USBPacket *packey, void *opaque)
/* NAK timeouts are only generated in Bulk transfers and
* Data-errors in Isochronous. */
if (ep->interrupt[1])
return musb_packet(s, ep, epnum, USB_TOKEN_IN,
packey->iov.size, musb_rx_packet_complete, 1);
if (ep->interrupt[1]) {
musb_packet(s, ep, epnum, USB_TOKEN_IN,
packey->iov.size, musb_rx_packet_complete, 1);
return;
}
ep->csr[1] |= MGC_M_RXCSR_DATAERROR;
if (!epnum)
@ -864,8 +868,7 @@ static void musb_tx_rdy(MUSBState *s, int epnum)
* but it doesn't make sense for us to do that. */
}
return musb_packet(s, ep, epnum, pid,
total, musb_tx_packet_complete, 0);
musb_packet(s, ep, epnum, pid, total, musb_tx_packet_complete, 0);
}
static void musb_rx_req(MUSBState *s, int epnum)
@ -929,8 +932,7 @@ static void musb_rx_req(MUSBState *s, int epnum)
}
#endif
return musb_packet(s, ep, epnum, USB_TOKEN_IN,
total, musb_rx_packet_complete, 1);
musb_packet(s, ep, epnum, USB_TOKEN_IN, total, musb_rx_packet_complete, 1);
}
static uint8_t musb_read_fifo(MUSBEndPoint *ep)

4
include/hw/elf_ops.h
View File

@ -315,7 +315,9 @@ static int glue(load_elf, SZ)(const char *name, int fd,
glue(load_symbols, SZ)(&ehdr, fd, must_swab, clear_lsb);
size = ehdr.e_phnum * sizeof(phdr[0]);
lseek(fd, ehdr.e_phoff, SEEK_SET);
if (lseek(fd, ehdr.e_phoff, SEEK_SET) != ehdr.e_phoff) {
goto fail;
}
phdr = g_malloc0(size);
if (!phdr)
goto fail;

2
include/qom/cpu.h
View File

@ -593,7 +593,7 @@ static inline void cpu_unaligned_access(CPUState *cpu, vaddr addr,
{
CPUClass *cc = CPU_GET_CLASS(cpu);
return cc->do_unaligned_access(cpu, addr, is_write, is_user, retaddr);
cc->do_unaligned_access(cpu, addr, is_write, is_user, retaddr);
}
#endif

8
monitor.c
View File

@ -4691,11 +4691,13 @@ static void monitor_find_completion_by_table(Monitor *mon,
if (cmd->sub_table) {
/* do the job again */
return monitor_find_completion_by_table(mon, cmd->sub_table,
&args[1], nb_args - 1);
monitor_find_completion_by_table(mon, cmd->sub_table,
&args[1], nb_args - 1);
return;
}
if (cmd->command_completion) {
return cmd->command_completion(mon->rs, nb_args, args[nb_args - 1]);
cmd->command_completion(mon->rs, nb_args, args[nb_args - 1]);
return;
}
ptype = next_arg_type(cmd->args_type);

4
qemu-options.hx
View File

@ -1403,7 +1403,7 @@ DEF("smbios", HAS_ARG, QEMU_OPTION_smbios,
" [,asset=str][,part=str]\n"
" specify SMBIOS type 4 fields\n"
"-smbios type=17[,loc_pfx=str][,bank=str][,manufacturer=str][,serial=str]\n"
" [,asset=str][,part=str]\n"
" [,asset=str][,part=str][,speed=%d]\n"
" specify SMBIOS type 17 fields\n",
QEMU_ARCH_I386)
STEXI
@ -1426,7 +1426,7 @@ Specify SMBIOS type 3 fields
@item -smbios type=4[,sock_pfx=@var{str}][,manufacturer=@var{str}][,version=@var{str}][,serial=@var{str}][,asset=@var{str}][,part=@var{str}]
Specify SMBIOS type 4 fields
@item -smbios type=17[,loc_pfx=@var{str}][,bank=@var{str}][,manufacturer=@var{str}][,serial=@var{str}][,asset=@var{str}][,part=@var{str}]
@item -smbios type=17[,loc_pfx=@var{str}][,bank=@var{str}][,manufacturer=@var{str}][,serial=@var{str}][,asset=@var{str}][,part=@var{str}][,speed=@var{%d}]
Specify SMBIOS type 17 fields
ETEXI

1
qga/commands-posix.c
View File

@ -2283,6 +2283,7 @@ GuestMemoryBlockInfo *qmp_guest_get_memory_block_info(Error **errp)
buf = g_malloc0(20);
ga_read_sysfs_file(dirfd, "block_size_bytes", buf, 20, &local_err);
close(dirfd);
if (local_err) {
g_free(buf);
error_propagate(errp, local_err);

4
qmp-commands.hx
View File

@ -276,7 +276,6 @@ EQMP
.args_type = "device:O",
.params = "driver[,prop=value][,...]",
.help = "add device, like -device on the command line",
.user_print = monitor_user_noop,
.mhandler.cmd_new = do_device_add,
},
@ -786,7 +785,6 @@ EQMP
.args_type = "protocol:s,hostname:s,port:i?,tls-port:i?,cert-subject:s?",
.params = "protocol hostname port tls-port cert-subject",
.help = "send migration info to spice/vnc client",
.user_print = monitor_user_noop,
.mhandler.cmd_async = client_migrate_info,
.flags = MONITOR_CMD_ASYNC,
},
@ -822,7 +820,6 @@ EQMP
.args_type = "paging:b,protocol:s,begin:i?,end:i?,format:s?",
.params = "-p protocol [begin] [length] [format]",
.help = "dump guest memory to file",
.user_print = monitor_user_noop,
.mhandler.cmd_new = qmp_marshal_input_dump_guest_memory,
},
@ -1862,7 +1859,6 @@ EQMP
.args_type = "",
.params = "",
.help = "enable QMP capabilities",
.user_print = monitor_user_noop,
.mhandler.cmd_new = do_qmp_capabilities,
},

2
qom/cpu.c
View File

@ -96,7 +96,7 @@ void cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list,
{
CPUClass *cc = CPU_GET_CLASS(cpu);
return cc->get_memory_mapping(cpu, list, errp);
cc->get_memory_mapping(cpu, list, errp);
}
static void cpu_common_get_memory_mapping(CPUState *cpu,

3
savevm.c
View File

@ -941,8 +941,7 @@ int qemu_loadvm_state(QEMUFile *f)
int file_error_after_eof = -1;
if (qemu_savevm_state_blocked(&local_err)) {
error_report("%s", error_get_pretty(local_err));
error_free(local_err);
error_report_err(local_err);
return -EINVAL;
}

10
target-cris/opcode-cris.h
View File

@ -108,16 +108,6 @@ struct cris_support_reg
};
extern const struct cris_support_reg cris_support_regs[];
struct cris_cond15
{
/* The name of the condition. */
const char *const name;
/* What CPU version this condition name applies to. */
enum cris_insn_version_usage applicable_version;
};
extern const struct cris_cond15 cris_conds15[];
/* Opcode-dependent constants. */
#define AUTOINCR_BIT (0x04)

2
target-mips/dsp_helper.c
View File

@ -3678,7 +3678,7 @@ void cpu_wrdsp(uint32_t rs, uint32_t mask_num, CPUMIPSState *env)
void helper_wrdsp(target_ulong rs, target_ulong mask_num, CPUMIPSState *env)
{
return cpu_wrdsp(rs, mask_num, env);
cpu_wrdsp(rs, mask_num, env);
}
uint32_t cpu_rddsp(uint32_t mask_num, CPUMIPSState *env)

10
target-moxie/mmu.h
View File

@ -6,11 +6,11 @@
typedef struct {
uint32_t phy;
uint32_t pfn;
int g:1;
int v:1;
int k:1;
int w:1;
int e:1;
unsigned g:1;
unsigned v:1;
unsigned k:1;
unsigned w:1;
unsigned e:1;
int cause_op;
} MoxieMMUResult;

22
target-tricore/translate.c
View File

@ -1111,7 +1111,7 @@ gen_m16add32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n)
TCGv temp2 = tcg_temp_new();
if (n == 0) {
tcg_gen_mul_tl(temp, arg2, arg3);
} else { /* n is exspected to be 1 */
} else { /* n is expected to be 1 */
tcg_gen_mul_tl(temp, arg2, arg3);
tcg_gen_shli_tl(temp, temp, 1);
/* catch special case r1 = r2 = 0x8000 */
@ -1131,7 +1131,7 @@ gen_m16adds32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n)
TCGv temp2 = tcg_temp_new();
if (n == 0) {
tcg_gen_mul_tl(temp, arg2, arg3);
} else { /* n is exspected to be 1 */
} else { /* n is expected to be 1 */
tcg_gen_mul_tl(temp, arg2, arg3);
tcg_gen_shli_tl(temp, temp, 1);
/* catch special case r1 = r2 = 0x8000 */
@ -1156,7 +1156,7 @@ gen_m16add64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
if (n == 0) {
tcg_gen_mul_tl(temp, arg2, arg3);
} else { /* n is exspected to be 1 */
} else { /* n is expected to be 1 */
tcg_gen_mul_tl(temp, arg2, arg3);
tcg_gen_shli_tl(temp, temp, 1);
/* catch special case r1 = r2 = 0x8000 */
@ -1188,7 +1188,7 @@ gen_m16adds64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
if (n == 0) {
tcg_gen_mul_tl(temp, arg2, arg3);
} else { /* n is exspected to be 1 */
} else { /* n is expected to be 1 */
tcg_gen_mul_tl(temp, arg2, arg3);
tcg_gen_shli_tl(temp, temp, 1);
/* catch special case r1 = r2 = 0x8000 */
@ -1975,7 +1975,7 @@ gen_m16sub32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n)
TCGv temp2 = tcg_temp_new();
if (n == 0) {
tcg_gen_mul_tl(temp, arg2, arg3);
} else { /* n is exspected to be 1 */
} else { /* n is expected to be 1 */
tcg_gen_mul_tl(temp, arg2, arg3);
tcg_gen_shli_tl(temp, temp, 1);
/* catch special case r1 = r2 = 0x8000 */
@ -1995,7 +1995,7 @@ gen_m16subs32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n)
TCGv temp2 = tcg_temp_new();
if (n == 0) {
tcg_gen_mul_tl(temp, arg2, arg3);
} else { /* n is exspected to be 1 */
} else { /* n is expected to be 1 */
tcg_gen_mul_tl(temp, arg2, arg3);
tcg_gen_shli_tl(temp, temp, 1);
/* catch special case r1 = r2 = 0x8000 */
@ -2020,7 +2020,7 @@ gen_m16sub64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
if (n == 0) {
tcg_gen_mul_tl(temp, arg2, arg3);
} else { /* n is exspected to be 1 */
} else { /* n is expected to be 1 */
tcg_gen_mul_tl(temp, arg2, arg3);
tcg_gen_shli_tl(temp, temp, 1);
/* catch special case r1 = r2 = 0x8000 */
@ -2052,7 +2052,7 @@ gen_m16subs64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
if (n == 0) {
tcg_gen_mul_tl(temp, arg2, arg3);
} else { /* n is exspected to be 1 */
} else { /* n is expected to be 1 */
tcg_gen_mul_tl(temp, arg2, arg3);
tcg_gen_shli_tl(temp, temp, 1);
/* catch special case r1 = r2 = 0x8000 */
@ -2560,7 +2560,7 @@ gen_mul_q(TCGv rl, TCGv rh, TCGv arg1, TCGv arg2, uint32_t n, uint32_t up_shift)
}
/* reset v bit */
tcg_gen_movi_tl(cpu_PSW_V, 0);
} else { /* n is exspected to be 1 */
} else { /* n is expected to be 1 */
tcg_gen_ext_i32_i64(temp_64, arg1);
tcg_gen_ext_i32_i64(temp2_64, arg2);
@ -2572,7 +2572,7 @@ gen_mul_q(TCGv rl, TCGv rh, TCGv arg1, TCGv arg2, uint32_t n, uint32_t up_shift)
tcg_gen_shri_i64(temp_64, temp_64, up_shift - 1);
}
tcg_gen_extr_i64_i32(rl, rh, temp_64);
/* overflow only occours if r1 = r2 = 0x8000 */
/* overflow only occurs if r1 = r2 = 0x8000 */
if (up_shift == 0) {/* result is 64 bit */
tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, rh,
0x80000000);
@ -2605,7 +2605,7 @@ gen_mul_q_16(TCGv ret, TCGv arg1, TCGv arg2, uint32_t n)
TCGv temp = tcg_temp_new();
if (n == 0) {
tcg_gen_mul_tl(ret, arg1, arg2);
} else { /* n is exspected to be 1 */
} else { /* n is expected to be 1 */
tcg_gen_mul_tl(ret, arg1, arg2);
tcg_gen_shli_tl(ret, ret, 1);
/* catch special case r1 = r2 = 0x8000 */

2
tests/ahci-test.c
View File

@ -583,7 +583,7 @@ static void ahci_test_port_spec(AHCIQState *ahci, uint8_t port)
ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_MPSP);
}
/* If, via CPD or MPSP we detect a drive, HPCP must be on. */
if (BITANY(reg, AHCI_PX_CMD_CPD || AHCI_PX_CMD_MPSP)) {
if (BITANY(reg, AHCI_PX_CMD_CPD | AHCI_PX_CMD_MPSP)) {
ASSERT_BIT_SET(reg, AHCI_PX_CMD_HPCP);
}
/* HPCP and ESP cannot both be active. */

6
vl.c
View File

@ -1012,6 +1012,7 @@ static int parse_add_fd(QemuOpts *opts, void *opaque)
int fd, dupfd, flags;
int64_t fdset_id;
const char *fd_opaque = NULL;
AddfdInfo *fdinfo;
fd = qemu_opt_get_number(opts, "fd", -1);
fdset_id = qemu_opt_get_number(opts, "set", -1);
@ -1061,8 +1062,9 @@ static int parse_add_fd(QemuOpts *opts, void *opaque)
}
/* add the duplicate fd, and optionally the opaque string, to the fd set */
monitor_fdset_add_fd(dupfd, true, fdset_id, fd_opaque ? true : false,
fd_opaque, NULL);
fdinfo = monitor_fdset_add_fd(dupfd, true, fdset_id, !!fd_opaque, fd_opaque,
&error_abort);
g_free(fdinfo);
return 0;
}