Hexagon (target/hexagon) load into shifted register instructions
The following instructions are added
L2_loadalignb_io Ryy32 = memb_fifo(Rs32+#s11:1)
L2_loadalignh_io Ryy32 = memh_fifo(Rs32+#s11:1)
L4_loadalignb_ur Ryy32 = memb_fifo(Rt32<<#u2+#U6)
L4_loadalignh_ur Ryy32 = memh_fifo(Rt32<<#u2+#U6)
L4_loadalignb_ap Ryy32 = memb_fifo(Re32=#U6)
L4_loadalignh_ap Ryy32 = memh_fifo(Re32=#U6)
L2_loadalignb_pr Ryy32 = memb_fifo(Rx32++Mu2)
L2_loadalignh_pr Ryy32 = memh_fifo(Rx32++Mu2)
L2_loadalignb_pbr Ryy32 = memb_fifo(Rx32++Mu2:brev)
L2_loadalignh_pbr Ryy32 = memh_fifo(Rx32++Mu2:brev)
L2_loadalignb_pi Ryy32 = memb_fifo(Rx32++#s4:1)
L2_loadalignh_pi Ryy32 = memh_fifo(Rx32++#s4:1)
L2_loadalignb_pci Ryy32 = memb_fifo(Rx32++#s4:1:circ(Mu2))
L2_loadalignh_pci Ryy32 = memh_fifo(Rx32++#s4:1:circ(Mu2))
L2_loadalignb_pcr Ryy32 = memb_fifo(Rx32++I:circ(Mu2))
L2_loadalignh_pcr Ryy32 = memh_fifo(Rx32++I:circ(Mu2))
Test cases in tests/tcg/hexagon/load_align.c
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <1617930474-31979-26-git-send-email-tsimpson@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Taylor Simpson
Richard Henderson
parent
0d0b91a804
commit
7aa9ffab79
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@ -260,6 +260,72 @@
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#define fGEN_TCG_L2_loadbsw4_pi(SHORTCODE) \
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fGEN_TCG_loadbXw4(GET_EA_pi, true)
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/*
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* These instructions load a half word, shift the destination right by 16 bits
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* and place the loaded value in the high half word of the destination pair.
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* The GET_EA macro determines the addressing mode.
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*/
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#define fGEN_TCG_loadalignh(GET_EA) \
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do { \
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TCGv tmp = tcg_temp_new(); \
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TCGv_i64 tmp_i64 = tcg_temp_new_i64(); \
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GET_EA; \
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fLOAD(1, 2, u, EA, tmp); \
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tcg_gen_extu_i32_i64(tmp_i64, tmp); \
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tcg_gen_shri_i64(RyyV, RyyV, 16); \
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tcg_gen_deposit_i64(RyyV, RyyV, tmp_i64, 48, 16); \
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tcg_temp_free(tmp); \
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tcg_temp_free_i64(tmp_i64); \
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} while (0)
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#define fGEN_TCG_L4_loadalignh_ur(SHORTCODE) \
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fGEN_TCG_loadalignh(fEA_IRs(UiV, RtV, uiV))
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#define fGEN_TCG_L2_loadalignh_io(SHORTCODE) \
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fGEN_TCG_loadalignh(fEA_RI(RsV, siV))
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#define fGEN_TCG_L2_loadalignh_pci(SHORTCODE) \
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fGEN_TCG_loadalignh(GET_EA_pci)
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#define fGEN_TCG_L2_loadalignh_pcr(SHORTCODE) \
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fGEN_TCG_loadalignh(GET_EA_pcr(1))
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#define fGEN_TCG_L4_loadalignh_ap(SHORTCODE) \
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fGEN_TCG_loadalignh(GET_EA_ap)
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#define fGEN_TCG_L2_loadalignh_pr(SHORTCODE) \
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fGEN_TCG_loadalignh(GET_EA_pr)
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#define fGEN_TCG_L2_loadalignh_pbr(SHORTCODE) \
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fGEN_TCG_loadalignh(GET_EA_pbr)
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#define fGEN_TCG_L2_loadalignh_pi(SHORTCODE) \
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fGEN_TCG_loadalignh(GET_EA_pi)
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/* Same as above, but loads a byte instead of half word */
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#define fGEN_TCG_loadalignb(GET_EA) \
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do { \
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TCGv tmp = tcg_temp_new(); \
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TCGv_i64 tmp_i64 = tcg_temp_new_i64(); \
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GET_EA; \
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fLOAD(1, 1, u, EA, tmp); \
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tcg_gen_extu_i32_i64(tmp_i64, tmp); \
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tcg_gen_shri_i64(RyyV, RyyV, 8); \
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tcg_gen_deposit_i64(RyyV, RyyV, tmp_i64, 56, 8); \
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tcg_temp_free(tmp); \
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tcg_temp_free_i64(tmp_i64); \
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} while (0)
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#define fGEN_TCG_L2_loadalignb_io(SHORTCODE) \
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fGEN_TCG_loadalignb(fEA_RI(RsV, siV))
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#define fGEN_TCG_L4_loadalignb_ur(SHORTCODE) \
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fGEN_TCG_loadalignb(fEA_IRs(UiV, RtV, uiV))
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#define fGEN_TCG_L2_loadalignb_pci(SHORTCODE) \
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fGEN_TCG_loadalignb(GET_EA_pci)
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#define fGEN_TCG_L2_loadalignb_pcr(SHORTCODE) \
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fGEN_TCG_loadalignb(GET_EA_pcr(0))
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#define fGEN_TCG_L4_loadalignb_ap(SHORTCODE) \
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fGEN_TCG_loadalignb(GET_EA_ap)
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#define fGEN_TCG_L2_loadalignb_pr(SHORTCODE) \
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fGEN_TCG_loadalignb(GET_EA_pr)
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#define fGEN_TCG_L2_loadalignb_pbr(SHORTCODE) \
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fGEN_TCG_loadalignb(GET_EA_pbr)
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#define fGEN_TCG_L2_loadalignb_pi(SHORTCODE) \
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fGEN_TCG_loadalignb(GET_EA_pi)
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/*
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* Predicated loads
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* Here is a primer to understand the tag names
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@ -348,6 +348,9 @@ STD_LD_ENC(bzw2,"0 011")
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STD_LD_ENC(bsw4,"0 111")
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STD_LD_ENC(bsw2,"0 001")
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STD_LDX_ENC(alignh,"0 010")
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STD_LDX_ENC(alignb,"0 100")
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STD_LD_ENC(rb, "1 000")
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STD_LD_ENC(rub, "1 001")
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STD_LD_ENC(rh, "1 010")
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@ -80,6 +80,25 @@ ATTRIBS(A_LOAD),"2",
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STD_LD_AMODES(loadalignh, "Ryy32=memh_fifo", "Load Half-word into shifted vector",
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ATTRIBS(A_LOAD),"1",
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{
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fHIDE(size8u_t tmpV;)
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fLOAD(1,2,u,EA,tmpV);
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RyyV = (((size8u_t)RyyV)>>16)|(tmpV<<48);
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},1)
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STD_LD_AMODES(loadalignb, "Ryy32=memb_fifo", "Load byte into shifted vector",
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ATTRIBS(A_LOAD),"0",
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{
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fHIDE(size8u_t tmpV;)
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fLOAD(1,1,u,EA,tmpV);
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RyyV = (((size8u_t)RyyV)>>8)|(tmpV<<56);
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},0)
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/* The set of addressing modes standard to all Store instructions */
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#define STD_ST_AMODES(TAG,DEST,OPER,DESCR,ATTRIB,SHFT,SEMANTICS,SCALE)\
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@ -45,6 +45,7 @@ HEX_TESTS += mem_noshuf
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HEX_TESTS += circ
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HEX_TESTS += brev
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HEX_TESTS += load_unpack
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HEX_TESTS += load_align
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HEX_TESTS += atomics
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HEX_TESTS += fpstuff
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@ -0,0 +1,415 @@
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/*
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* Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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/*
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* Test load align instructions
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*
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* Example
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* r1:0 = memh_fifo(r1+#0)
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* loads a half word from memory, shifts the destination register
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* right by one half word and inserts the loaded value into the high
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* half word of the destination.
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*
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* There are 8 addressing modes and byte and half word variants, for a
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* total of 16 instructions to test
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*/
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#include <stdio.h>
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#include <string.h>
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int err;
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char buf[16] __attribute__((aligned(1 << 16)));
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void init_buf(void)
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{
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int i;
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for (i = 0; i < 16; i++) {
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buf[i] = i + 1;
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}
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}
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void __check(int line, long long result, long long expect)
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{
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if (result != expect) {
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printf("ERROR at line %d: 0x%016llx != 0x%016llx\n",
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line, result, expect);
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err++;
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}
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}
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#define check(RES, EXP) __check(__LINE__, RES, EXP)
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void __checkp(int line, void *p, void *expect)
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{
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if (p != expect) {
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printf("ERROR at line %d: 0x%p != 0x%p\n", line, p, expect);
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err++;
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}
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}
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#define checkp(RES, EXP) __checkp(__LINE__, RES, EXP)
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/*
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****************************************************************************
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* _io addressing mode (addr + offset)
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*/
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#define LOAD_io(SZ, RES, ADDR, OFF) \
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__asm__( \
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"%0 = mem" #SZ "_fifo(%1+#" #OFF ")\n\t" \
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: "+r"(RES) \
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: "r"(ADDR))
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#define LOAD_io_b(RES, ADDR, OFF) \
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LOAD_io(b, RES, ADDR, OFF)
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#define LOAD_io_h(RES, ADDR, OFF) \
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LOAD_io(h, RES, ADDR, OFF)
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#define TEST_io(NAME, SZ, SIZE, EXP1, EXP2, EXP3, EXP4) \
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void test_##NAME(void) \
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{ \
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long long result = ~0LL; \
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LOAD_io_##SZ(result, buf, 0 * (SIZE)); \
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check(result, (EXP1)); \
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LOAD_io_##SZ(result, buf, 1 * (SIZE)); \
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check(result, (EXP2)); \
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LOAD_io_##SZ(result, buf, 2 * (SIZE)); \
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check(result, (EXP3)); \
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LOAD_io_##SZ(result, buf, 3 * (SIZE)); \
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check(result, (EXP4)); \
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}
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TEST_io(loadalignb_io, b, 1,
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0x01ffffffffffffffLL, 0x0201ffffffffffffLL,
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0x030201ffffffffffLL, 0x04030201ffffffffLL)
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TEST_io(loadalignh_io, h, 2,
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0x0201ffffffffffffLL, 0x04030201ffffffffLL,
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0x060504030201ffffLL, 0x0807060504030201LL)
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/*
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****************************************************************************
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* _ur addressing mode (index << offset + base)
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*/
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#define LOAD_ur(SZ, RES, SHIFT, IDX) \
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__asm__( \
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"%0 = mem" #SZ "_fifo(%1<<#" #SHIFT " + ##buf)\n\t" \
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: "+r"(RES) \
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: "r"(IDX))
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#define LOAD_ur_b(RES, SHIFT, IDX) \
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LOAD_ur(b, RES, SHIFT, IDX)
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#define LOAD_ur_h(RES, SHIFT, IDX) \
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LOAD_ur(h, RES, SHIFT, IDX)
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#define TEST_ur(NAME, SZ, SHIFT, RES1, RES2, RES3, RES4) \
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void test_##NAME(void) \
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{ \
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long long result = ~0LL; \
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LOAD_ur_##SZ(result, (SHIFT), 0); \
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check(result, (RES1)); \
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LOAD_ur_##SZ(result, (SHIFT), 1); \
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check(result, (RES2)); \
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LOAD_ur_##SZ(result, (SHIFT), 2); \
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check(result, (RES3)); \
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LOAD_ur_##SZ(result, (SHIFT), 3); \
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check(result, (RES4)); \
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}
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TEST_ur(loadalignb_ur, b, 1,
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0x01ffffffffffffffLL, 0x0301ffffffffffffLL,
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0x050301ffffffffffLL, 0x07050301ffffffffLL)
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TEST_ur(loadalignh_ur, h, 1,
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0x0201ffffffffffffLL, 0x04030201ffffffffLL,
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0x060504030201ffffLL, 0x0807060504030201LL)
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/*
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****************************************************************************
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* _ap addressing mode (addr = base)
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*/
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#define LOAD_ap(SZ, RES, PTR, ADDR) \
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__asm__( \
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"%0 = mem" #SZ "_fifo(%1 = ##" #ADDR ")\n\t" \
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: "+r"(RES), "=r"(PTR))
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#define LOAD_ap_b(RES, PTR, ADDR) \
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LOAD_ap(b, RES, PTR, ADDR)
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#define LOAD_ap_h(RES, PTR, ADDR) \
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LOAD_ap(h, RES, PTR, ADDR)
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#define TEST_ap(NAME, SZ, SIZE, RES1, RES2, RES3, RES4) \
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void test_##NAME(void) \
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{ \
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long long result = ~0LL; \
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void *ptr; \
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LOAD_ap_##SZ(result, ptr, (buf + 0 * (SIZE))); \
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check(result, (RES1)); \
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checkp(ptr, &buf[0 * (SIZE)]); \
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LOAD_ap_##SZ(result, ptr, (buf + 1 * (SIZE))); \
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check(result, (RES2)); \
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checkp(ptr, &buf[1 * (SIZE)]); \
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LOAD_ap_##SZ(result, ptr, (buf + 2 * (SIZE))); \
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check(result, (RES3)); \
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checkp(ptr, &buf[2 * (SIZE)]); \
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LOAD_ap_##SZ(result, ptr, (buf + 3 * (SIZE))); \
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check(result, (RES4)); \
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checkp(ptr, &buf[3 * (SIZE)]); \
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}
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TEST_ap(loadalignb_ap, b, 1,
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0x01ffffffffffffffLL, 0x0201ffffffffffffLL,
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0x030201ffffffffffLL, 0x04030201ffffffffLL)
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TEST_ap(loadalignh_ap, h, 2,
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0x0201ffffffffffffLL, 0x04030201ffffffffLL,
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0x060504030201ffffLL, 0x0807060504030201LL)
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/*
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****************************************************************************
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* _rp addressing mode (addr ++ modifer-reg)
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*/
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#define LOAD_pr(SZ, RES, PTR, INC) \
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__asm__( \
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"m0 = %2\n\t" \
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"%0 = mem" #SZ "_fifo(%1++m0)\n\t" \
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: "+r"(RES), "+r"(PTR) \
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: "r"(INC) \
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: "m0")
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#define LOAD_pr_b(RES, PTR, INC) \
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LOAD_pr(b, RES, PTR, INC)
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#define LOAD_pr_h(RES, PTR, INC) \
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LOAD_pr(h, RES, PTR, INC)
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#define TEST_pr(NAME, SZ, SIZE, RES1, RES2, RES3, RES4) \
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void test_##NAME(void) \
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{ \
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long long result = ~0LL; \
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void *ptr = buf; \
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LOAD_pr_##SZ(result, ptr, (SIZE)); \
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check(result, (RES1)); \
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checkp(ptr, &buf[1 * (SIZE)]); \
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LOAD_pr_##SZ(result, ptr, (SIZE)); \
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check(result, (RES2)); \
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checkp(ptr, &buf[2 * (SIZE)]); \
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LOAD_pr_##SZ(result, ptr, (SIZE)); \
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check(result, (RES3)); \
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checkp(ptr, &buf[3 * (SIZE)]); \
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LOAD_pr_##SZ(result, ptr, (SIZE)); \
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check(result, (RES4)); \
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checkp(ptr, &buf[4 * (SIZE)]); \
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}
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TEST_pr(loadalignb_pr, b, 1,
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0x01ffffffffffffffLL, 0x0201ffffffffffffLL,
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0x030201ffffffffffLL, 0x04030201ffffffffLL)
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TEST_pr(loadalignh_pr, h, 2,
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0x0201ffffffffffffLL, 0x04030201ffffffffLL,
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0x060504030201ffffLL, 0x0807060504030201LL)
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/*
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****************************************************************************
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* _pbr addressing mode (addr ++ modifer-reg:brev)
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*/
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#define LOAD_pbr(SZ, RES, PTR) \
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__asm__( \
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"r4 = #(1 << (16 - 3))\n\t" \
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"m0 = r4\n\t" \
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"%0 = mem" #SZ "_fifo(%1++m0:brev)\n\t" \
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: "+r"(RES), "+r"(PTR) \
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: \
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: "r4", "m0")
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#define LOAD_pbr_b(RES, PTR) \
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LOAD_pbr(b, RES, PTR)
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#define LOAD_pbr_h(RES, PTR) \
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LOAD_pbr(h, RES, PTR)
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#define TEST_pbr(NAME, SZ, RES1, RES2, RES3, RES4) \
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void test_##NAME(void) \
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{ \
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long long result = ~0LL; \
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void *ptr = buf; \
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LOAD_pbr_##SZ(result, ptr); \
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check(result, (RES1)); \
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LOAD_pbr_##SZ(result, ptr); \
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check(result, (RES2)); \
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LOAD_pbr_##SZ(result, ptr); \
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check(result, (RES3)); \
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LOAD_pbr_##SZ(result, ptr); \
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check(result, (RES4)); \
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}
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TEST_pbr(loadalignb_pbr, b,
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0x01ffffffffffffffLL, 0x0501ffffffffffffLL,
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0x030501ffffffffffLL, 0x07030501ffffffffLL)
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TEST_pbr(loadalignh_pbr, h,
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0x0201ffffffffffffLL, 0x06050201ffffffffLL,
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0x040306050201ffffLL, 0x0807040306050201LL)
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/*
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****************************************************************************
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* _pi addressing mode (addr ++ inc)
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*/
|
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#define LOAD_pi(SZ, RES, PTR, INC) \
|
||||
__asm__( \
|
||||
"%0 = mem" #SZ "_fifo(%1++#" #INC ")\n\t" \
|
||||
: "+r"(RES), "+r"(PTR))
|
||||
#define LOAD_pi_b(RES, PTR, INC) \
|
||||
LOAD_pi(b, RES, PTR, INC)
|
||||
#define LOAD_pi_h(RES, PTR, INC) \
|
||||
LOAD_pi(h, RES, PTR, INC)
|
||||
|
||||
#define TEST_pi(NAME, SZ, INC, RES1, RES2, RES3, RES4) \
|
||||
void test_##NAME(void) \
|
||||
{ \
|
||||
long long result = ~0LL; \
|
||||
void *ptr = buf; \
|
||||
LOAD_pi_##SZ(result, ptr, (INC)); \
|
||||
check(result, (RES1)); \
|
||||
checkp(ptr, &buf[1 * (INC)]); \
|
||||
LOAD_pi_##SZ(result, ptr, (INC)); \
|
||||
check(result, (RES2)); \
|
||||
checkp(ptr, &buf[2 * (INC)]); \
|
||||
LOAD_pi_##SZ(result, ptr, (INC)); \
|
||||
check(result, (RES3)); \
|
||||
checkp(ptr, &buf[3 * (INC)]); \
|
||||
LOAD_pi_##SZ(result, ptr, (INC)); \
|
||||
check(result, (RES4)); \
|
||||
checkp(ptr, &buf[4 * (INC)]); \
|
||||
}
|
||||
|
||||
TEST_pi(loadalignb_pi, b, 1,
|
||||
0x01ffffffffffffffLL, 0x0201ffffffffffffLL,
|
||||
0x030201ffffffffffLL, 0x04030201ffffffffLL)
|
||||
TEST_pi(loadalignh_pi, h, 2,
|
||||
0x0201ffffffffffffLL, 0x04030201ffffffffLL,
|
||||
0x060504030201ffffLL, 0x0807060504030201LL)
|
||||
|
||||
/*
|
||||
****************************************************************************
|
||||
* _pci addressing mode (addr ++ inc:circ)
|
||||
*/
|
||||
#define LOAD_pci(SZ, RES, PTR, START, LEN, INC) \
|
||||
__asm__( \
|
||||
"r4 = %3\n\t" \
|
||||
"m0 = r4\n\t" \
|
||||
"cs0 = %2\n\t" \
|
||||
"%0 = mem" #SZ "_fifo(%1++#" #INC ":circ(m0))\n\t" \
|
||||
: "+r"(RES), "+r"(PTR) \
|
||||
: "r"(START), "r"(LEN) \
|
||||
: "r4", "m0", "cs0")
|
||||
#define LOAD_pci_b(RES, PTR, START, LEN, INC) \
|
||||
LOAD_pci(b, RES, PTR, START, LEN, INC)
|
||||
#define LOAD_pci_h(RES, PTR, START, LEN, INC) \
|
||||
LOAD_pci(h, RES, PTR, START, LEN, INC)
|
||||
|
||||
#define TEST_pci(NAME, SZ, LEN, INC, RES1, RES2, RES3, RES4) \
|
||||
void test_##NAME(void) \
|
||||
{ \
|
||||
long long result = ~0LL; \
|
||||
void *ptr = buf; \
|
||||
LOAD_pci_##SZ(result, ptr, buf, (LEN), (INC)); \
|
||||
check(result, (RES1)); \
|
||||
checkp(ptr, &buf[(1 * (INC)) % (LEN)]); \
|
||||
LOAD_pci_##SZ(result, ptr, buf, (LEN), (INC)); \
|
||||
check(result, (RES2)); \
|
||||
checkp(ptr, &buf[(2 * (INC)) % (LEN)]); \
|
||||
LOAD_pci_##SZ(result, ptr, buf, (LEN), (INC)); \
|
||||
check(result, (RES3)); \
|
||||
checkp(ptr, &buf[(3 * (INC)) % (LEN)]); \
|
||||
LOAD_pci_##SZ(result, ptr, buf, (LEN), (INC)); \
|
||||
check(result, (RES4)); \
|
||||
checkp(ptr, &buf[(4 * (INC)) % (LEN)]); \
|
||||
}
|
||||
|
||||
TEST_pci(loadalignb_pci, b, 2, 1,
|
||||
0x01ffffffffffffffLL, 0x0201ffffffffffffLL,
|
||||
0x010201ffffffffffLL, 0x02010201ffffffffLL)
|
||||
TEST_pci(loadalignh_pci, h, 4, 2,
|
||||
0x0201ffffffffffffLL, 0x04030201ffffffffLL,
|
||||
0x020104030201ffffLL, 0x0403020104030201LL)
|
||||
|
||||
/*
|
||||
****************************************************************************
|
||||
* _pcr addressing mode (addr ++ I:circ(modifier-reg))
|
||||
*/
|
||||
#define LOAD_pcr(SZ, RES, PTR, START, LEN, INC) \
|
||||
__asm__( \
|
||||
"r4 = %2\n\t" \
|
||||
"m1 = r4\n\t" \
|
||||
"cs1 = %3\n\t" \
|
||||
"%0 = mem" #SZ "_fifo(%1++I:circ(m1))\n\t" \
|
||||
: "+r"(RES), "+r"(PTR) \
|
||||
: "r"((((INC) & 0x7f) << 17) | ((LEN) & 0x1ffff)), \
|
||||
"r"(START) \
|
||||
: "r4", "m1", "cs1")
|
||||
#define LOAD_pcr_b(RES, PTR, START, LEN, INC) \
|
||||
LOAD_pcr(b, RES, PTR, START, LEN, INC)
|
||||
#define LOAD_pcr_h(RES, PTR, START, LEN, INC) \
|
||||
LOAD_pcr(h, RES, PTR, START, LEN, INC)
|
||||
|
||||
#define TEST_pcr(NAME, SZ, SIZE, LEN, INC, RES1, RES2, RES3, RES4) \
|
||||
void test_##NAME(void) \
|
||||
{ \
|
||||
long long result = ~0LL; \
|
||||
void *ptr = buf; \
|
||||
LOAD_pcr_##SZ(result, ptr, buf, (LEN), (INC)); \
|
||||
check(result, (RES1)); \
|
||||
checkp(ptr, &buf[(1 * (INC) * (SIZE)) % (LEN)]); \
|
||||
LOAD_pcr_##SZ(result, ptr, buf, (LEN), (INC)); \
|
||||
check(result, (RES2)); \
|
||||
checkp(ptr, &buf[(2 * (INC) * (SIZE)) % (LEN)]); \
|
||||
LOAD_pcr_##SZ(result, ptr, buf, (LEN), (INC)); \
|
||||
check(result, (RES3)); \
|
||||
checkp(ptr, &buf[(3 * (INC) * (SIZE)) % (LEN)]); \
|
||||
LOAD_pcr_##SZ(result, ptr, buf, (LEN), (INC)); \
|
||||
check(result, (RES4)); \
|
||||
checkp(ptr, &buf[(4 * (INC) * (SIZE)) % (LEN)]); \
|
||||
}
|
||||
|
||||
TEST_pcr(loadalignb_pcr, b, 1, 2, 1,
|
||||
0x01ffffffffffffffLL, 0x0201ffffffffffffLL,
|
||||
0x010201ffffffffffLL, 0x02010201ffffffffLL)
|
||||
TEST_pcr(loadalignh_pcr, h, 2, 4, 1,
|
||||
0x0201ffffffffffffLL, 0x04030201ffffffffLL,
|
||||
0x020104030201ffffLL, 0x0403020104030201LL)
|
||||
|
||||
int main()
|
||||
{
|
||||
init_buf();
|
||||
|
||||
test_loadalignb_io();
|
||||
test_loadalignh_io();
|
||||
|
||||
test_loadalignb_ur();
|
||||
test_loadalignh_ur();
|
||||
|
||||
test_loadalignb_ap();
|
||||
test_loadalignh_ap();
|
||||
|
||||
test_loadalignb_pr();
|
||||
test_loadalignh_pr();
|
||||
|
||||
test_loadalignb_pbr();
|
||||
test_loadalignh_pbr();
|
||||
|
||||
test_loadalignb_pi();
|
||||
test_loadalignh_pi();
|
||||
|
||||
test_loadalignb_pci();
|
||||
test_loadalignh_pci();
|
||||
|
||||
test_loadalignb_pcr();
|
||||
test_loadalignh_pcr();
|
||||
|
||||
puts(err ? "FAIL" : "PASS");
|
||||
return err ? 1 : 0;
|
||||
}
|
||||
Loading…
Reference in New Issue