From 7c00edb9a2e2cb975a60e80dbe1e66287a9d5777 Mon Sep 17 00:00:00 2001 From: Marcin Nowakowski Date: Thu, 16 Feb 2023 06:17:15 +0100 Subject: [PATCH] target/mips: Fix SWM32 handling for microMIPS MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit SWM32 should store a sequence of 32-bit words from the GPRs, but it was incorrectly coded to store 16-bit words only. As a result, an LWM32 that usually follows would restore invalid register values. Fixes: 7dd547e5ab ("target/mips: Use cpu_*_mmuidx_ra instead of MMU_MODE*_SUFFIX") Signed-off-by: Marcin Nowakowski Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20230216051717.3911212-3-marcin.nowakowski@fungible.com> Signed-off-by: Philippe Mathieu-Daudé --- target/mips/tcg/ldst_helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/mips/tcg/ldst_helper.c b/target/mips/tcg/ldst_helper.c index d0bd0267b2..c1a8380e34 100644 --- a/target/mips/tcg/ldst_helper.c +++ b/target/mips/tcg/ldst_helper.c @@ -248,14 +248,14 @@ void helper_swm(CPUMIPSState *env, target_ulong addr, target_ulong reglist, target_ulong i; for (i = 0; i < base_reglist; i++) { - cpu_stw_mmuidx_ra(env, addr, env->active_tc.gpr[multiple_regs[i]], + cpu_stl_mmuidx_ra(env, addr, env->active_tc.gpr[multiple_regs[i]], mem_idx, GETPC()); addr += 4; } } if (do_r31) { - cpu_stw_mmuidx_ra(env, addr, env->active_tc.gpr[31], mem_idx, GETPC()); + cpu_stl_mmuidx_ra(env, addr, env->active_tc.gpr[31], mem_idx, GETPC()); } }