OpenE2K/qemu-e2k
13
4
Fork 0
Code Issues 4 Pull Requests Projects 2 Releases Activity

target/arm: Implement M-profile VPR register

Browse Source 
If MVE is implemented for an M-profile CPU then it has a VPR
register, which tracks predication information.

Implement the read and write handling of this register, and
the migration of its state.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210520152840.24453-7-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2021-05-20 16:28:37 +01:00
parent 300137965d
commit 7c3d47dab9
3 changed files with 63 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
target/arm/cpu.h
View File

@ -564,6 +564,7 @@ typedef struct CPUARMState {
uint32_t cpacr[M_REG_NUM_BANKS];
uint32_t nsacr;
int ltpsize;
uint32_t vpr;
} v7m;
/* Information associated with an exception about to be taken:
@ -1761,6 +1762,11 @@ FIELD(V7M_FPCCR, ASPEN, 31, 1)
R_V7M_FPCCR_UFRDY_MASK | \
R_V7M_FPCCR_ASPEN_MASK)
/* v7M VPR bits */
FIELD(V7M_VPR, P0, 0, 16)
FIELD(V7M_VPR, MASK01, 16, 4)
FIELD(V7M_VPR, MASK23, 20, 4)
/*
* System register ID fields.
*/

19
target/arm/machine.c
View File

@ -318,6 +318,24 @@ static const VMStateDescription vmstate_m_fp = {
}
};
static bool mve_needed(void *opaque)
{
ARMCPU *cpu = opaque;
return cpu_isar_feature(aa32_mve, cpu);
}
static const VMStateDescription vmstate_m_mve = {
.name = "cpu/m/mve",
.version_id = 1,
.minimum_version_id = 1,
.needed = mve_needed,
.fields = (VMStateField[]) {
VMSTATE_UINT32(env.v7m.vpr, ARMCPU),
VMSTATE_END_OF_LIST()
},
};
static const VMStateDescription vmstate_m = {
.name = "cpu/m",
.version_id = 4,
@ -344,6 +362,7 @@ static const VMStateDescription vmstate_m = {
&vmstate_m_other_sp,
&vmstate_m_v8m,
&vmstate_m_fp,
&vmstate_m_mve,
NULL
}
};

38
target/arm/translate-vfp.c
View File

@ -703,6 +703,12 @@ static FPSysRegCheckResult fp_sysreg_checks(DisasContext *s, int regno)
return FPSysRegCheckFailed;
}
break;
case ARM_VFP_VPR:
case ARM_VFP_P0:
if (!dc_isar_feature(aa32_mve, s)) {
return FPSysRegCheckFailed;
}
break;
default:
return FPSysRegCheckFailed;
}
@ -817,6 +823,25 @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int regno,
tcg_temp_free_i32(sfpa);
break;
}
case ARM_VFP_VPR:
/* Behaves as NOP if not privileged */
if (IS_USER(s)) {
break;
}
tmp = loadfn(s, opaque);
store_cpu_field(tmp, v7m.vpr);
break;
case ARM_VFP_P0:
{
TCGv_i32 vpr;
tmp = loadfn(s, opaque);
vpr = load_cpu_field(v7m.vpr);
tcg_gen_deposit_i32(vpr, vpr, tmp,
R_V7M_VPR_P0_SHIFT, R_V7M_VPR_P0_LENGTH);
store_cpu_field(vpr, v7m.vpr);
tcg_temp_free_i32(tmp);
break;
}
default:
g_assert_not_reached();
}
@ -935,6 +960,19 @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int regno,
tcg_temp_free_i32(fpscr);
break;
}
case ARM_VFP_VPR:
/* Behaves as NOP if not privileged */
if (IS_USER(s)) {
break;
}
tmp = load_cpu_field(v7m.vpr);
storefn(s, opaque, tmp);
break;
case ARM_VFP_P0:
tmp = load_cpu_field(v7m.vpr);
tcg_gen_extract_i32(tmp, tmp, R_V7M_VPR_P0_SHIFT, R_V7M_VPR_P0_LENGTH);
storefn(s, opaque, tmp);
break;
default:
g_assert_not_reached();
}