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target-arm: A64: Add SIMD TBL/TBLX

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Add support for the SIMD TBL/TBLX instructions (group C3.6.2).

Signed-off-by: Michael Matz <matz@suse.de>
[PMM: rewritten to do more of the decode in translate-a64.c,
 and to do only one 64 bit pass at a time in the helper]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Michael Matz 2014-01-31 14:47:31 +00:00 committed by Peter Maydell
parent 5c73747f3c
commit 7c51048fa9
3 changed files with 86 additions and 1 deletions
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31
target-arm/helper-a64.c
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@ -122,3 +122,34 @@ uint64_t HELPER(vfp_cmped_a64)(float64 x, float64 y, void *fp_status)
{
return float_rel_to_flags(float64_compare(x, y, fp_status));
}
uint64_t HELPER(simd_tbl)(CPUARMState *env, uint64_t result, uint64_t indices,
uint32_t rn, uint32_t numregs)
{
/* Helper function for SIMD TBL and TBX. We have to do the table
* lookup part for the 64 bits worth of indices we're passed in.
* result is the initial results vector (either zeroes for TBL
* or some guest values for TBX), rn the register number where
* the table starts, and numregs the number of registers in the table.
* We return the results of the lookups.
*/
int shift;
for (shift = 0; shift < 64; shift += 8) {
int index = extract64(indices, shift, 8);
if (index < 16 * numregs) {
/* Convert index (a byte offset into the virtual table
* which is a series of 128-bit vectors concatenated)
* into the correct vfp.regs[] element plus a bit offset
* into that element, bearing in mind that the table
* can wrap around from V31 to V0.
*/
int elt = (rn * 2 + (index >> 3)) % 64;
int bitidx = (index & 7) * 8;
uint64_t val = extract64(env->vfp.regs[elt], bitidx, 8);
result = deposit64(result, shift, 8, val);
}
}
return result;
}

1
target-arm/helper-a64.h
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@ -26,3 +26,4 @@ DEF_HELPER_3(vfp_cmps_a64, i64, f32, f32, ptr)
DEF_HELPER_3(vfp_cmpes_a64, i64, f32, f32, ptr)
DEF_HELPER_3(vfp_cmpd_a64, i64, f64, f64, ptr)
DEF_HELPER_3(vfp_cmped_a64, i64, f64, f64, ptr)
DEF_HELPER_FLAGS_5(simd_tbl, TCG_CALL_NO_RWG_SE, i64, env, i64, i64, i32, i32)

55
target-arm/translate-a64.c
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@ -4742,7 +4742,60 @@ static void disas_simd_ext(DisasContext *s, uint32_t insn)
*/
static void disas_simd_tb(DisasContext *s, uint32_t insn)
{
unsupported_encoding(s, insn);
int op2 = extract32(insn, 22, 2);
int is_q = extract32(insn, 30, 1);
int rm = extract32(insn, 16, 5);
int rn = extract32(insn, 5, 5);
int rd = extract32(insn, 0, 5);
int is_tblx = extract32(insn, 12, 1);
int len = extract32(insn, 13, 2);
TCGv_i64 tcg_resl, tcg_resh, tcg_idx;
TCGv_i32 tcg_regno, tcg_numregs;
if (op2 != 0) {
unallocated_encoding(s);
return;
}
/* This does a table lookup: for every byte element in the input
* we index into a table formed from up to four vector registers,
* and then the output is the result of the lookups. Our helper
* function does the lookup operation for a single 64 bit part of
* the input.
*/
tcg_resl = tcg_temp_new_i64();
tcg_resh = tcg_temp_new_i64();
if (is_tblx) {
read_vec_element(s, tcg_resl, rd, 0, MO_64);
} else {
tcg_gen_movi_i64(tcg_resl, 0);
}
if (is_tblx && is_q) {
read_vec_element(s, tcg_resh, rd, 1, MO_64);
} else {
tcg_gen_movi_i64(tcg_resh, 0);
}
tcg_idx = tcg_temp_new_i64();
tcg_regno = tcg_const_i32(rn);
tcg_numregs = tcg_const_i32(len + 1);
read_vec_element(s, tcg_idx, rm, 0, MO_64);
gen_helper_simd_tbl(tcg_resl, cpu_env, tcg_resl, tcg_idx,
tcg_regno, tcg_numregs);
if (is_q) {
read_vec_element(s, tcg_idx, rm, 1, MO_64);
gen_helper_simd_tbl(tcg_resh, cpu_env, tcg_resh, tcg_idx,
tcg_regno, tcg_numregs);
}
tcg_temp_free_i64(tcg_idx);
tcg_temp_free_i32(tcg_regno);
tcg_temp_free_i32(tcg_numregs);
write_vec_element(s, tcg_resl, rd, 0, MO_64);
tcg_temp_free_i64(tcg_resl);
write_vec_element(s, tcg_resh, rd, 1, MO_64);
tcg_temp_free_i64(tcg_resh);
}
/* C3.6.3 ZIP/UZP/TRN