bcm2835_peripherals: add rollup device for bcm2835 peripherals
This device maintains all the non-CPU peripherals on bcm2835 (Pi1) which are also present on bcm2836 (Pi2). It also implements the private address spaces used for DMA and mailboxes. Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Signed-off-by: Andrew Baumann <Andrew.Baumann@microsoft.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Andrew Baumann
Peter Maydell
parent
e3ece3e34d
commit
7c62aeb82a
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@ -11,6 +11,7 @@ obj-y += armv7m.o exynos4210.o pxa2xx.o pxa2xx_gpio.o pxa2xx_pic.o
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obj-$(CONFIG_DIGIC) += digic.o
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obj-y += omap1.o omap2.o strongarm.o
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obj-$(CONFIG_ALLWINNER_A10) += allwinner-a10.o cubieboard.o
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obj-$(CONFIG_RASPI) += bcm2835_peripherals.o
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obj-$(CONFIG_STM32F205_SOC) += stm32f205_soc.o
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obj-$(CONFIG_XLNX_ZYNQMP) += xlnx-zynqmp.o xlnx-ep108.o
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obj-$(CONFIG_FSL_IMX25) += fsl-imx25.o imx25_pdk.o
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@ -0,0 +1,204 @@
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/*
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* Raspberry Pi emulation (c) 2012 Gregory Estrade
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* Upstreaming code cleanup [including bcm2835_*] (c) 2013 Jan Petrous
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*
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* Rasperry Pi 2 emulation and refactoring Copyright (c) 2015, Microsoft
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* Written by Andrew Baumann
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*
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* This code is licensed under the GNU GPLv2 and later.
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*/
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#include "hw/arm/bcm2835_peripherals.h"
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#include "hw/misc/bcm2835_mbox_defs.h"
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#include "hw/arm/raspi_platform.h"
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/* Peripheral base address on the VC (GPU) system bus */
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#define BCM2835_VC_PERI_BASE 0x7e000000
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/* Capabilities for SD controller: no DMA, high-speed, default clocks etc. */
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#define BCM2835_SDHC_CAPAREG 0x52034b4
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static void bcm2835_peripherals_init(Object *obj)
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{
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BCM2835PeripheralState *s = BCM2835_PERIPHERALS(obj);
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/* Memory region for peripheral devices, which we export to our parent */
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memory_region_init(&s->peri_mr, obj,"bcm2835-peripherals", 0x1000000);
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object_property_add_child(obj, "peripheral-io", OBJECT(&s->peri_mr), NULL);
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sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->peri_mr);
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/* Internal memory region for peripheral bus addresses (not exported) */
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memory_region_init(&s->gpu_bus_mr, obj, "bcm2835-gpu", (uint64_t)1 << 32);
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object_property_add_child(obj, "gpu-bus", OBJECT(&s->gpu_bus_mr), NULL);
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/* Internal memory region for request/response communication with
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* mailbox-addressable peripherals (not exported)
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*/
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memory_region_init(&s->mbox_mr, obj, "bcm2835-mbox",
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MBOX_CHAN_COUNT << MBOX_AS_CHAN_SHIFT);
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/* Interrupt Controller */
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object_initialize(&s->ic, sizeof(s->ic), TYPE_BCM2835_IC);
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object_property_add_child(obj, "ic", OBJECT(&s->ic), NULL);
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qdev_set_parent_bus(DEVICE(&s->ic), sysbus_get_default());
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/* UART0 */
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s->uart0 = SYS_BUS_DEVICE(object_new("pl011"));
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object_property_add_child(obj, "uart0", OBJECT(s->uart0), NULL);
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qdev_set_parent_bus(DEVICE(s->uart0), sysbus_get_default());
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/* Mailboxes */
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object_initialize(&s->mboxes, sizeof(s->mboxes), TYPE_BCM2835_MBOX);
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object_property_add_child(obj, "mbox", OBJECT(&s->mboxes), NULL);
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qdev_set_parent_bus(DEVICE(&s->mboxes), sysbus_get_default());
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object_property_add_const_link(OBJECT(&s->mboxes), "mbox-mr",
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OBJECT(&s->mbox_mr), &error_abort);
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/* Property channel */
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object_initialize(&s->property, sizeof(s->property), TYPE_BCM2835_PROPERTY);
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object_property_add_child(obj, "property", OBJECT(&s->property), NULL);
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qdev_set_parent_bus(DEVICE(&s->property), sysbus_get_default());
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object_property_add_const_link(OBJECT(&s->property), "dma-mr",
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OBJECT(&s->gpu_bus_mr), &error_abort);
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/* Extended Mass Media Controller */
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object_initialize(&s->sdhci, sizeof(s->sdhci), TYPE_SYSBUS_SDHCI);
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object_property_add_child(obj, "sdhci", OBJECT(&s->sdhci), NULL);
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qdev_set_parent_bus(DEVICE(&s->sdhci), sysbus_get_default());
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}
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static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
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{
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BCM2835PeripheralState *s = BCM2835_PERIPHERALS(dev);
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Object *obj;
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MemoryRegion *ram;
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Error *err = NULL;
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uint32_t ram_size;
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int n;
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obj = object_property_get_link(OBJECT(dev), "ram", &err);
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if (obj == NULL) {
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error_setg(errp, "%s: required ram link not found: %s",
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__func__, error_get_pretty(err));
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return;
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}
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ram = MEMORY_REGION(obj);
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ram_size = memory_region_size(ram);
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/* Map peripherals and RAM into the GPU address space. */
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memory_region_init_alias(&s->peri_mr_alias, OBJECT(s),
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"bcm2835-peripherals", &s->peri_mr, 0,
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memory_region_size(&s->peri_mr));
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memory_region_add_subregion_overlap(&s->gpu_bus_mr, BCM2835_VC_PERI_BASE,
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&s->peri_mr_alias, 1);
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/* RAM is aliased four times (different cache configurations) on the GPU */
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for (n = 0; n < 4; n++) {
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memory_region_init_alias(&s->ram_alias[n], OBJECT(s),
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"bcm2835-gpu-ram-alias[*]", ram, 0, ram_size);
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memory_region_add_subregion_overlap(&s->gpu_bus_mr, (hwaddr)n << 30,
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&s->ram_alias[n], 0);
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}
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/* Interrupt Controller */
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object_property_set_bool(OBJECT(&s->ic), true, "realized", &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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memory_region_add_subregion(&s->peri_mr, ARMCTRL_IC_OFFSET,
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sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->ic), 0));
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sysbus_pass_irq(SYS_BUS_DEVICE(s), SYS_BUS_DEVICE(&s->ic));
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/* UART0 */
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object_property_set_bool(OBJECT(s->uart0), true, "realized", &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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memory_region_add_subregion(&s->peri_mr, UART0_OFFSET,
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sysbus_mmio_get_region(s->uart0, 0));
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sysbus_connect_irq(s->uart0, 0,
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qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ,
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INTERRUPT_UART));
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/* Mailboxes */
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object_property_set_bool(OBJECT(&s->mboxes), true, "realized", &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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memory_region_add_subregion(&s->peri_mr, ARMCTRL_0_SBM_OFFSET,
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sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->mboxes), 0));
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->mboxes), 0,
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qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_ARM_IRQ,
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INTERRUPT_ARM_MAILBOX));
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/* Property channel */
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object_property_set_int(OBJECT(&s->property), ram_size, "ram-size", &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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object_property_set_bool(OBJECT(&s->property), true, "realized", &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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memory_region_add_subregion(&s->mbox_mr,
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MBOX_CHAN_PROPERTY << MBOX_AS_CHAN_SHIFT,
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sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->property), 0));
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->property), 0,
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qdev_get_gpio_in(DEVICE(&s->mboxes), MBOX_CHAN_PROPERTY));
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/* Extended Mass Media Controller */
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object_property_set_int(OBJECT(&s->sdhci), BCM2835_SDHC_CAPAREG, "capareg",
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&err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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object_property_set_bool(OBJECT(&s->sdhci), true, "realized", &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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memory_region_add_subregion(&s->peri_mr, EMMC_OFFSET,
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sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->sdhci), 0));
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0,
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qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ,
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INTERRUPT_ARASANSDIO));
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}
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static void bcm2835_peripherals_class_init(ObjectClass *oc, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(oc);
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dc->realize = bcm2835_peripherals_realize;
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}
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static const TypeInfo bcm2835_peripherals_type_info = {
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.name = TYPE_BCM2835_PERIPHERALS,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(BCM2835PeripheralState),
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.instance_init = bcm2835_peripherals_init,
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.class_init = bcm2835_peripherals_class_init,
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};
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static void bcm2835_peripherals_register_types(void)
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{
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type_register_static(&bcm2835_peripherals_type_info);
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}
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type_init(bcm2835_peripherals_register_types)
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@ -0,0 +1,42 @@
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/*
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* Raspberry Pi emulation (c) 2012 Gregory Estrade
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* Upstreaming code cleanup [including bcm2835_*] (c) 2013 Jan Petrous
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*
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* Rasperry Pi 2 emulation and refactoring Copyright (c) 2015, Microsoft
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* Written by Andrew Baumann
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*
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* This code is licensed under the GNU GPLv2 and later.
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*/
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#ifndef BCM2835_PERIPHERALS_H
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#define BCM2835_PERIPHERALS_H
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#include "qemu-common.h"
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#include "exec/address-spaces.h"
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#include "hw/sysbus.h"
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#include "hw/intc/bcm2835_ic.h"
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#include "hw/misc/bcm2835_property.h"
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#include "hw/misc/bcm2835_mbox.h"
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#include "hw/sd/sdhci.h"
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#define TYPE_BCM2835_PERIPHERALS "bcm2835-peripherals"
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#define BCM2835_PERIPHERALS(obj) \
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OBJECT_CHECK(BCM2835PeripheralState, (obj), TYPE_BCM2835_PERIPHERALS)
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typedef struct BCM2835PeripheralState {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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MemoryRegion peri_mr, peri_mr_alias, gpu_bus_mr, mbox_mr;
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MemoryRegion ram_alias[4];
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qemu_irq irq, fiq;
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SysBusDevice *uart0;
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BCM2835ICState ic;
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BCM2835PropertyState property;
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BCM2835MboxState mboxes;
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SDHCIState sdhci;
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} BCM2835PeripheralState;
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#endif /* BCM2835_PERIPHERALS_H */
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@ -0,0 +1,128 @@
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/*
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* bcm2708 aka bcm2835/2836 aka Raspberry Pi/Pi2 SoC platform defines
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*
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* These definitions are derived from those in Raspbian Linux at
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* arch/arm/mach-{bcm2708,bcm2709}/include/mach/platform.h
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* where they carry the following notice:
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*
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* Copyright (C) 2010 Broadcom
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#define MCORE_OFFSET 0x0000 /* Fake frame buffer device
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* (the multicore sync block) */
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#define IC0_OFFSET 0x2000
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#define ST_OFFSET 0x3000 /* System Timer */
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#define MPHI_OFFSET 0x6000 /* Message-based Parallel Host Intf. */
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#define DMA_OFFSET 0x7000 /* DMA controller, channels 0-14 */
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#define ARM_OFFSET 0xB000 /* BCM2708 ARM control block */
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#define ARMCTRL_OFFSET (ARM_OFFSET + 0x000)
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#define ARMCTRL_IC_OFFSET (ARM_OFFSET + 0x200) /* Interrupt controller */
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#define ARMCTRL_TIMER0_1_OFFSET (ARM_OFFSET + 0x400) /* Timer 0 and 1 */
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#define ARMCTRL_0_SBM_OFFSET (ARM_OFFSET + 0x800) /* User 0 (ARM) Semaphores
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* Doorbells & Mailboxes */
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#define PM_OFFSET 0x100000 /* Power Management, Reset controller
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* and Watchdog registers */
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#define PCM_CLOCK_OFFSET 0x101098
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#define RNG_OFFSET 0x104000
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#define GPIO_OFFSET 0x200000
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#define UART0_OFFSET 0x201000
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#define MMCI0_OFFSET 0x202000
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#define I2S_OFFSET 0x203000
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#define SPI0_OFFSET 0x204000
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#define BSC0_OFFSET 0x205000 /* BSC0 I2C/TWI */
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#define UART1_OFFSET 0x215000
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#define EMMC_OFFSET 0x300000
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#define SMI_OFFSET 0x600000
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#define BSC1_OFFSET 0x804000 /* BSC1 I2C/TWI */
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#define USB_OFFSET 0x980000 /* DTC_OTG USB controller */
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#define DMA15_OFFSET 0xE05000 /* DMA controller, channel 15 */
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/* GPU interrupts */
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#define INTERRUPT_TIMER0 0
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#define INTERRUPT_TIMER1 1
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#define INTERRUPT_TIMER2 2
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#define INTERRUPT_TIMER3 3
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#define INTERRUPT_CODEC0 4
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#define INTERRUPT_CODEC1 5
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#define INTERRUPT_CODEC2 6
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#define INTERRUPT_JPEG 7
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#define INTERRUPT_ISP 8
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#define INTERRUPT_USB 9
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#define INTERRUPT_3D 10
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#define INTERRUPT_TRANSPOSER 11
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#define INTERRUPT_MULTICORESYNC0 12
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#define INTERRUPT_MULTICORESYNC1 13
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#define INTERRUPT_MULTICORESYNC2 14
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#define INTERRUPT_MULTICORESYNC3 15
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#define INTERRUPT_DMA0 16
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#define INTERRUPT_DMA1 17
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#define INTERRUPT_DMA2 18
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#define INTERRUPT_DMA3 19
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#define INTERRUPT_DMA4 20
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#define INTERRUPT_DMA5 21
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#define INTERRUPT_DMA6 22
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#define INTERRUPT_DMA7 23
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#define INTERRUPT_DMA8 24
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#define INTERRUPT_DMA9 25
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#define INTERRUPT_DMA10 26
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#define INTERRUPT_DMA11 27
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#define INTERRUPT_DMA12 28
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#define INTERRUPT_AUX 29
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#define INTERRUPT_ARM 30
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#define INTERRUPT_VPUDMA 31
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#define INTERRUPT_HOSTPORT 32
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#define INTERRUPT_VIDEOSCALER 33
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#define INTERRUPT_CCP2TX 34
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#define INTERRUPT_SDC 35
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#define INTERRUPT_DSI0 36
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#define INTERRUPT_AVE 37
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#define INTERRUPT_CAM0 38
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#define INTERRUPT_CAM1 39
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#define INTERRUPT_HDMI0 40
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#define INTERRUPT_HDMI1 41
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#define INTERRUPT_PIXELVALVE1 42
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#define INTERRUPT_I2CSPISLV 43
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#define INTERRUPT_DSI1 44
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#define INTERRUPT_PWA0 45
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#define INTERRUPT_PWA1 46
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#define INTERRUPT_CPR 47
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#define INTERRUPT_SMI 48
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#define INTERRUPT_GPIO0 49
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#define INTERRUPT_GPIO1 50
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#define INTERRUPT_GPIO2 51
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#define INTERRUPT_GPIO3 52
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#define INTERRUPT_I2C 53
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#define INTERRUPT_SPI 54
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#define INTERRUPT_I2SPCM 55
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#define INTERRUPT_SDIO 56
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#define INTERRUPT_UART 57
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#define INTERRUPT_SLIMBUS 58
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#define INTERRUPT_VEC 59
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#define INTERRUPT_CPG 60
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#define INTERRUPT_RNG 61
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#define INTERRUPT_ARASANSDIO 62
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#define INTERRUPT_AVSPMON 63
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/* ARM CPU IRQs use a private number space */
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#define INTERRUPT_ARM_TIMER 0
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#define INTERRUPT_ARM_MAILBOX 1
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#define INTERRUPT_ARM_DOORBELL_0 2
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#define INTERRUPT_ARM_DOORBELL_1 3
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#define INTERRUPT_VPU0_HALTED 4
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#define INTERRUPT_VPU1_HALTED 5
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#define INTERRUPT_ILLEGAL_TYPE0 6
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#define INTERRUPT_ILLEGAL_TYPE1 7
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