piix_pci: kill PIIX3IrqState
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
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0358718275
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7cd9eee0f6
@ -36,18 +36,14 @@ typedef PCIHostState I440FXState;
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typedef struct PIIX3State {
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PCIDevice dev;
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int pci_irq_levels[4];
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} PIIX3State;
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typedef struct PIIX3IrqState {
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PIIX3State *piix3;
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qemu_irq *pic;
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} PIIX3IrqState;
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} PIIX3State;
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struct PCII440FXState {
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PCIDevice dev;
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target_phys_addr_t isa_page_descs[384 / 4];
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uint8_t smm_enabled;
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PIIX3IrqState *irq_state;
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PIIX3State *piix3;
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};
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static void i440fx_addr_writel(void* opaque, uint32_t addr, uint32_t val)
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@ -167,7 +163,7 @@ static int i440fx_load_old(QEMUFile* f, void *opaque, int version_id)
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if (version_id == 2)
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for (i = 0; i < 4; i++)
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d->irq_state->piix3->pci_irq_levels[i] = qemu_get_be32(f);
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d->piix3->pci_irq_levels[i] = qemu_get_be32(f);
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return 0;
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}
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@ -232,23 +228,24 @@ PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix3_devfn, qemu_irq *
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PCIBus *b;
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PCIDevice *d;
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I440FXState *s;
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PIIX3IrqState *irq_state = qemu_malloc(sizeof(*irq_state));
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PIIX3State *piix3;
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irq_state->pic = pic;
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dev = qdev_create(NULL, "i440FX-pcihost");
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s = FROM_SYSBUS(I440FXState, sysbus_from_qdev(dev));
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b = pci_register_bus(&s->busdev.qdev, "pci.0",
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piix3_set_irq, pci_slot_get_pirq, irq_state, 0, 4);
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b = pci_bus_new(&s->busdev.qdev, NULL, 0);
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s->bus = b;
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qdev_init(dev);
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d = pci_create_simple(b, 0, "i440FX");
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*pi440fx_state = DO_UPCAST(PCII440FXState, dev, d);
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(*pi440fx_state)->irq_state = irq_state;
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irq_state->piix3 = DO_UPCAST(PIIX3State, dev,
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piix3 = DO_UPCAST(PIIX3State, dev,
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pci_create_simple(b, -1, "PIIX3"));
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*piix3_devfn = irq_state->piix3->dev.devfn;
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piix3->pic = pic;
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pci_bus_irqs(b, piix3_set_irq, pci_slot_get_pirq, piix3, 4);
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(*pi440fx_state)->piix3 = piix3;
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*piix3_devfn = piix3->dev.devfn;
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return b;
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}
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@ -258,22 +255,22 @@ PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix3_devfn, qemu_irq *
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static void piix3_set_irq(void *opaque, int irq_num, int level)
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{
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int i, pic_irq, pic_level;
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PIIX3IrqState *irq_state = opaque;
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PIIX3State *piix3 = opaque;
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irq_state->piix3->pci_irq_levels[irq_num] = level;
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piix3->pci_irq_levels[irq_num] = level;
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/* now we change the pic irq level according to the piix irq mappings */
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/* XXX: optimize */
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pic_irq = irq_state->piix3->dev.config[0x60 + irq_num];
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pic_irq = piix3->dev.config[0x60 + irq_num];
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if (pic_irq < 16) {
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/* The pic level is the logical OR of all the PCI irqs mapped
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to it */
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pic_level = 0;
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for (i = 0; i < 4; i++) {
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if (pic_irq == irq_state->piix3->dev.config[0x60 + i])
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pic_level |= irq_state->piix3->pci_irq_levels[i];
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if (pic_irq == piix3->dev.config[0x60 + i])
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pic_level |= piix3->pci_irq_levels[i];
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}
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qemu_set_irq(irq_state->pic[pic_irq], pic_level);
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qemu_set_irq(piix3->pic[pic_irq], pic_level);
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}
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}
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