target/ppc: Add POWER10 DD1.0 model information
This includes in QEMU a new CPU model for the POWER10 processor with the same capabilities of a POWER9 process. The model will be extended when support is completed. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20191205184454.10722-2-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
This commit is contained in:
Cédric Le Goater
David Gibson
parent
2b6dda81c3
commit
7d37b274ff
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@ -51,36 +51,38 @@ static const CompatInfo compat_table[] = {
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{ /* POWER6, ISA2.05 */
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.name = "power6",
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.pvr = CPU_POWERPC_LOGICAL_2_05,
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.pcr = PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | PCR_COMPAT_2_06 |
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PCR_COMPAT_2_05 | PCR_TM_DIS | PCR_VSX_DIS,
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.pcr = PCR_COMPAT_3_10 | PCR_COMPAT_3_00 | PCR_COMPAT_2_07 |
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PCR_COMPAT_2_06 | PCR_COMPAT_2_05 | PCR_TM_DIS | PCR_VSX_DIS,
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.pcr_level = PCR_COMPAT_2_05,
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.max_vthreads = 2,
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},
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{ /* POWER7, ISA2.06 */
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.name = "power7",
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.pvr = CPU_POWERPC_LOGICAL_2_06,
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.pcr = PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_TM_DIS,
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.pcr = PCR_COMPAT_3_10 | PCR_COMPAT_3_00 | PCR_COMPAT_2_07 |
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PCR_COMPAT_2_06 | PCR_TM_DIS,
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.pcr_level = PCR_COMPAT_2_06,
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.max_vthreads = 4,
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},
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{
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.name = "power7+",
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.pvr = CPU_POWERPC_LOGICAL_2_06_PLUS,
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.pcr = PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_TM_DIS,
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.pcr = PCR_COMPAT_3_10 | PCR_COMPAT_3_00 | PCR_COMPAT_2_07 |
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PCR_COMPAT_2_06 | PCR_TM_DIS,
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.pcr_level = PCR_COMPAT_2_06,
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.max_vthreads = 4,
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},
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{ /* POWER8, ISA2.07 */
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.name = "power8",
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.pvr = CPU_POWERPC_LOGICAL_2_07,
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.pcr = PCR_COMPAT_3_00 | PCR_COMPAT_2_07,
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.pcr = PCR_COMPAT_3_10 | PCR_COMPAT_3_00 | PCR_COMPAT_2_07,
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.pcr_level = PCR_COMPAT_2_07,
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.max_vthreads = 8,
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},
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{ /* POWER9, ISA3.00 */
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.name = "power9",
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.pvr = CPU_POWERPC_LOGICAL_3_00,
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.pcr = PCR_COMPAT_3_00,
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.pcr = PCR_COMPAT_3_10 | PCR_COMPAT_3_00,
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.pcr_level = PCR_COMPAT_3_00,
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/*
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* POWER9 hardware only supports 4 threads / core, but this
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@ -91,6 +93,13 @@ static const CompatInfo compat_table[] = {
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*/
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.max_vthreads = 8,
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},
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{ /* POWER10, ISA3.10 */
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.name = "power10",
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.pvr = CPU_POWERPC_LOGICAL_3_10,
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.pcr = PCR_COMPAT_3_10,
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.pcr_level = PCR_COMPAT_3_10,
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.max_vthreads = 8,
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},
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};
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static const CompatInfo *compat_by_pvr(uint32_t pvr)
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@ -774,6 +774,8 @@
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"POWER9 v1.0")
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POWERPC_DEF("power9_v2.0", CPU_POWERPC_POWER9_DD20, POWER9,
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"POWER9 v2.0")
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POWERPC_DEF("power10_v1.0", CPU_POWERPC_POWER10_DD1, POWER10,
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"POWER10 v1.0")
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#endif /* defined (TARGET_PPC64) */
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/***************************************************************************/
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@ -950,6 +952,7 @@ PowerPCCPUAlias ppc_cpu_aliases[] = {
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{ "power8", "power8_v2.0" },
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{ "power8nvl", "power8nvl_v1.0" },
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{ "power9", "power9_v2.0" },
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{ "power10", "power10_v1.0" },
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#endif
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/* Generic PowerPCs */
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@ -373,6 +373,8 @@ enum {
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CPU_POWERPC_POWER9_BASE = 0x004E0000,
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CPU_POWERPC_POWER9_DD1 = 0x004E0100,
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CPU_POWERPC_POWER9_DD20 = 0x004E1200,
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CPU_POWERPC_POWER10_BASE = 0x00800000,
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CPU_POWERPC_POWER10_DD1 = 0x00800100,
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CPU_POWERPC_970_v22 = 0x00390202,
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CPU_POWERPC_970FX_v10 = 0x00391100,
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CPU_POWERPC_970FX_v20 = 0x003C0200,
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@ -409,6 +411,7 @@ enum {
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CPU_POWERPC_LOGICAL_2_06_PLUS = 0x0F100003,
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CPU_POWERPC_LOGICAL_2_07 = 0x0F000004,
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CPU_POWERPC_LOGICAL_3_00 = 0x0F000005,
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CPU_POWERPC_LOGICAL_3_10 = 0x0F000006,
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};
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/* System version register (used on MPC 8xxx) */
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@ -2364,6 +2364,7 @@ enum {
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PCR_COMPAT_2_06 = PPC_BIT(61),
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PCR_COMPAT_2_07 = PPC_BIT(60),
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PCR_COMPAT_3_00 = PPC_BIT(59),
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PCR_COMPAT_3_10 = PPC_BIT(58),
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PCR_VEC_DIS = PPC_BIT(0), /* Vec. disable (bit NA since POWER8) */
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PCR_VSX_DIS = PPC_BIT(1), /* VSX disable (bit NA since POWER8) */
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PCR_TM_DIS = PPC_BIT(2), /* Trans. memory disable (POWER8) */
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@ -3354,6 +3354,11 @@ static void init_excp_POWER9(CPUPPCState *env)
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#endif
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}
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static void init_excp_POWER10(CPUPPCState *env)
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{
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init_excp_POWER9(env);
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}
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#endif
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/*****************************************************************************/
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@ -8996,6 +9001,216 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data)
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pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE;
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}
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#ifdef CONFIG_SOFTMMU
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/*
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* Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-encodings
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* Encoded as array of int_32s in the form:
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* 0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy
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* x -> AP encoding
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* y -> radix mode supported page size (encoded as a shift)
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*/
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static struct ppc_radix_page_info POWER10_radix_page_info = {
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.count = 4,
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.entries = {
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0x0000000c, /* 4K - enc: 0x0 */
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0xa0000010, /* 64K - enc: 0x5 */
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0x20000015, /* 2M - enc: 0x1 */
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0x4000001e /* 1G - enc: 0x2 */
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}
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};
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#endif /* CONFIG_SOFTMMU */
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static void init_proc_POWER10(CPUPPCState *env)
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{
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/* Common Registers */
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init_proc_book3s_common(env);
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gen_spr_book3s_207_dbg(env);
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/* POWER8 Specific Registers */
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gen_spr_book3s_ids(env);
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gen_spr_amr(env);
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gen_spr_iamr(env);
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gen_spr_book3s_purr(env);
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gen_spr_power5p_common(env);
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gen_spr_power5p_lpar(env);
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gen_spr_power5p_ear(env);
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gen_spr_power6_common(env);
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gen_spr_power6_dbg(env);
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gen_spr_power8_tce_address_control(env);
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gen_spr_power8_ids(env);
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gen_spr_power8_ebb(env);
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gen_spr_power8_fscr(env);
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gen_spr_power8_pmu_sup(env);
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gen_spr_power8_pmu_user(env);
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gen_spr_power8_tm(env);
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gen_spr_power8_pspb(env);
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gen_spr_vtb(env);
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gen_spr_power8_ic(env);
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gen_spr_power8_book4(env);
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gen_spr_power8_rpr(env);
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gen_spr_power9_mmu(env);
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/* POWER9 Specific registers */
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spr_register_kvm(env, SPR_TIDR, "TIDR", NULL, NULL,
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spr_read_generic, spr_write_generic,
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KVM_REG_PPC_TIDR, 0);
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/* FIXME: Filter fields properly based on privilege level */
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spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL,
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spr_read_generic, spr_write_generic,
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KVM_REG_PPC_PSSCR, 0);
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/* env variables */
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env->dcache_line_size = 128;
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env->icache_line_size = 128;
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/* Allocate hardware IRQ controller */
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init_excp_POWER10(env);
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ppcPOWER9_irq_init(env_archcpu(env));
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}
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static bool ppc_pvr_match_power10(PowerPCCPUClass *pcc, uint32_t pvr)
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{
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if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER10_BASE) {
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return true;
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}
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return false;
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}
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static bool cpu_has_work_POWER10(CPUState *cs)
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{
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PowerPCCPU *cpu = POWERPC_CPU(cs);
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CPUPPCState *env = &cpu->env;
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if (cs->halted) {
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uint64_t psscr = env->spr[SPR_PSSCR];
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if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) {
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return false;
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}
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/* If EC is clear, just return true on any pending interrupt */
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if (!(psscr & PSSCR_EC)) {
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return true;
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}
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/* External Exception */
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if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) &&
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(env->spr[SPR_LPCR] & LPCR_EEE)) {
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bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC);
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if (heic == 0 || !msr_hv || msr_pr) {
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return true;
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}
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}
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/* Decrementer Exception */
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if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) &&
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(env->spr[SPR_LPCR] & LPCR_DEE)) {
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return true;
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}
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/* Machine Check or Hypervisor Maintenance Exception */
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if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK |
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1u << PPC_INTERRUPT_HMI)) && (env->spr[SPR_LPCR] & LPCR_OEE)) {
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return true;
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}
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/* Privileged Doorbell Exception */
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if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) &&
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(env->spr[SPR_LPCR] & LPCR_PDEE)) {
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return true;
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}
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/* Hypervisor Doorbell Exception */
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if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) &&
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(env->spr[SPR_LPCR] & LPCR_HDEE)) {
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return true;
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}
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/* Hypervisor virtualization exception */
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if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HVIRT)) &&
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(env->spr[SPR_LPCR] & LPCR_HVEE)) {
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return true;
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}
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if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) {
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return true;
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}
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return false;
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} else {
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return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
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}
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}
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POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(oc);
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PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
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CPUClass *cc = CPU_CLASS(oc);
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dc->fw_name = "PowerPC,POWER10";
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dc->desc = "POWER10";
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dc->props = powerpc_servercpu_properties;
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pcc->pvr_match = ppc_pvr_match_power10;
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pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07 |
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PCR_COMPAT_3_00;
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pcc->pcr_supported = PCR_COMPAT_3_10 | PCR_COMPAT_3_00 | PCR_COMPAT_2_07 |
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PCR_COMPAT_2_06 | PCR_COMPAT_2_05;
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pcc->init_proc = init_proc_POWER10;
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pcc->check_pow = check_pow_nocheck;
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cc->has_work = cpu_has_work_POWER10;
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pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
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PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
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PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
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PPC_FLOAT_FRSQRTES |
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PPC_FLOAT_STFIWX |
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PPC_FLOAT_EXT |
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PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
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PPC_MEM_SYNC | PPC_MEM_EIEIO |
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PPC_MEM_TLBSYNC |
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PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC |
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PPC_SEGMENT_64B | PPC_SLBI |
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PPC_POPCNTB | PPC_POPCNTWD |
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PPC_CILDST;
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pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX |
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PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
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PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
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PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
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PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
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PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
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PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL;
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pcc->msr_mask = (1ull << MSR_SF) |
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(1ull << MSR_SHV) |
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(1ull << MSR_TM) |
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(1ull << MSR_VR) |
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(1ull << MSR_VSX) |
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(1ull << MSR_EE) |
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(1ull << MSR_PR) |
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(1ull << MSR_FP) |
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(1ull << MSR_ME) |
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(1ull << MSR_FE0) |
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(1ull << MSR_SE) |
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(1ull << MSR_DE) |
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(1ull << MSR_FE1) |
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(1ull << MSR_IR) |
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(1ull << MSR_DR) |
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(1ull << MSR_PMM) |
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(1ull << MSR_RI) |
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(1ull << MSR_LE);
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pcc->mmu_model = POWERPC_MMU_3_00;
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#if defined(CONFIG_SOFTMMU)
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pcc->handle_mmu_fault = ppc64_v3_handle_mmu_fault;
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/* segment page size remain the same */
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pcc->hash64_opts = &ppc_hash64_opts_POWER7;
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pcc->radix_page_info = &POWER10_radix_page_info;
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pcc->lrg_decr_bits = 56;
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#endif
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pcc->excp_model = POWERPC_EXCP_POWER9;
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pcc->bus_model = PPC_FLAGS_INPUT_POWER9;
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pcc->bfd_mach = bfd_mach_ppc64;
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pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
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POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
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POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
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POWERPC_FLAG_VSX | POWERPC_FLAG_TM;
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pcc->l1_dcache_size = 0x8000;
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pcc->l1_icache_size = 0x8000;
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pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
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pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE;
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}
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#if !defined(CONFIG_USER_ONLY)
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void cpu_ppc_set_vhyp(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp)
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{
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