tcg/e2k: rename load mnemonics
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8f15399214
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7d5fa73732
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@ -75,10 +75,10 @@ DEF(SB, 1, 0x0000, 0x24000000, 0, 0, 1, 0, 0, 1)
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DEF(SH, 1, 0x0000, 0x25000000, 0, 0, 1, 0, 0, 1)
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DEF(SW, 1, 0x0000, 0x26000000, 0, 0, 1, 0, 0, 1)
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DEF(SD, 1, 0x0000, 0x27000000, 0, 0, 1, 0, 0, 1)
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DEF(LB, 3, 0x0000, 0x64000000, 1, 0, 1, 1, 0, 1)
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DEF(LH, 3, 0x0000, 0x65000000, 1, 0, 1, 1, 0, 1)
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DEF(LW, 3, 0x0000, 0x66000000, 1, 0, 1, 1, 0, 1)
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DEF(LD, 3, 0x0000, 0x67000000, 1, 0, 1, 1, 0, 1)
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DEF(LBU, 3, 0x0000, 0x64000000, 1, 0, 1, 1, 0, 1)
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DEF(LHU, 3, 0x0000, 0x65000000, 1, 0, 1, 1, 0, 1)
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DEF(LWU, 3, 0x0000, 0x66000000, 1, 0, 1, 1, 0, 1)
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DEF(LDU, 3, 0x0000, 0x67000000, 1, 0, 1, 1, 0, 1)
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DEF(MOVTD, 1, 0x0000, 0x61c00000, 1, 1, 0, 1, 1, 0)
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DEF(MOVTD_CTPR, 9, 0x0000, 0x61c00000, 1, 0, 0, 0, 0, 0)
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DEF(MULW, 6, 0x01c0, 0x20000000, 1, 1, 0, 1, 1, 0)
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@ -1249,7 +1249,7 @@ static void tcg_out_deposit_int(TCGContext *s, TCGType type, TCGReg ret,
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static void e2k_out_ld(Bundle *bundle, int alc, TCGType type, TCGReg ret,
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TCGReg addr, intptr_t offset)
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{
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AlcOpc opc = type == TCG_TYPE_I32 ? ALC_LW : ALC_LD;
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AlcOpc opc = type == TCG_TYPE_I32 ? ALC_LWU : ALC_LDU;
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e2k_out_alf1_rri(bundle, alc, opc, ret, addr, offset);
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}
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@ -1574,10 +1574,10 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg ret,
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tcg_debug_assert((opc & MO_BSWAP) == 0);
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switch (opc & MO_SIZE) {
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case MO_8: ldopc = ALC_LB; break;
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case MO_16: ldopc = ALC_LH; break;
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case MO_32: ldopc = ALC_LW; break;
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case MO_64: ldopc = ALC_LD; break;
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case MO_8: ldopc = ALC_LBU; break;
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case MO_16: ldopc = ALC_LHU; break;
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case MO_32: ldopc = ALC_LWU; break;
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case MO_64: ldopc = ALC_LDU; break;
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default:
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g_assert_not_reached();
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}
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@ -1672,7 +1672,7 @@ static void tcg_out_goto_tb(TCGContext *s, int which)
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tcg_out_ct(s, CTPR1, CT_ALWAYS, 0);
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/* When branch is out of range, fall through to indirect. */
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AlcOpc opc = TCG_TYPE_PTR == TCG_TYPE_I32 ? ALC_LW : ALC_LD;
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AlcOpc opc = TCG_TYPE_PTR == TCG_TYPE_I32 ? ALC_LWU : ALC_LDU;
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tcg_out_alf1_rii(s, 0, opc, TCG_REG_TMP0, 0, get_jmp_target_addr(s, which));
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tcg_out_prep_r(s, CTPR1, TCG_REG_TMP0);
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tcg_out_ct(s, CTPR1, CT_ALWAYS, 0);
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@ -1725,31 +1725,33 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
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case INDEX_op_ld8u_i32:
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case INDEX_op_ld8u_i64:
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tcg_out_alf1_rri(s, 0, ALC_LB, a0, a1, a2);
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tcg_out_alf1_rri(s, 0, ALC_LBU, a0, a1, a2);
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break;
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case INDEX_op_ld16u_i32:
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case INDEX_op_ld16u_i64:
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tcg_out_alf1_rri(s, 0, ALC_LH, a0, a1, a2);
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tcg_out_alf1_rri(s, 0, ALC_LHU, a0, a1, a2);
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break;
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case INDEX_op_ld32u_i64:
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tcg_out_alf1_rri(s, 0, ALC_LW, a0, a1, a2);
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tcg_out_alf1_rri(s, 0, ALC_LWU, a0, a1, a2);
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break;
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case INDEX_op_ld_i64:
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tcg_out_alf1_rri(s, 0, ALC_LD, a0, a1, a2);
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tcg_out_alf1_rri(s, 0, ALC_LDU, a0, a1, a2);
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break;
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case INDEX_op_ld8s_i32:
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case INDEX_op_ld8s_i64:
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tcg_out_alf1_rri(s, 0, ALC_LB, a0, a1, a2);
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tcg_out_alf1_rri(s, 0, ALC_LBU, a0, a1, a2);
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tcg_out_alf2_rr(s, 0, ALC_SXTB, a0, a0);
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break;
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case INDEX_op_ld16s_i32:
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case INDEX_op_ld16s_i64:
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tcg_out_alf1_rri(s, 0, ALC_LH, a0, a1, a2);
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tcg_out_alf1_rri(s, 0, ALC_LHU, a0, a1, a2);
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tcg_out_alf2_rr(s, 0, ALC_SXTH, a0, a0);
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break;
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case INDEX_op_ld_i32:
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tcg_out_alf1_rri(s, 0, ALC_LWU, a0, a1, a2);
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break;
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case INDEX_op_ld32s_i64:
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tcg_out_alf1_rri(s, 0, ALC_LW, a0, a1, a2);
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tcg_out_alf1_rri(s, 0, ALC_LWU, a0, a1, a2);
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tcg_out_alf2_rr(s, 0, ALC_SXTW, a0, a0);
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break;
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