From 7d7fb11615809839ff858328134c6a0abad27ea4 Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Mon, 22 Aug 2022 15:12:30 +0100 Subject: [PATCH] target/riscv: Honour -semihosting-config userspace=on and enable=on The riscv target incorrectly enabled semihosting always, whether the user asked for it or not. Call semihosting_enabled() passing the correct value to the is_userspace argument, which fixes this and also handles the userspace=on argument. Because we do this at translate time, we no longer need to check the privilege level in riscv_cpu_do_interrupt(). Note that this is a behaviour change: we used to default to semihosting being enabled, and now the user must pass "-semihosting-config enable=on" if they want it. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-Id: <20220822141230.3658237-8-peter.maydell@linaro.org> Signed-off-by: Richard Henderson --- target/riscv/cpu_helper.c | 9 +++------ target/riscv/insn_trans/trans_privileged.c.inc | 3 ++- target/riscv/translate.c | 1 + 3 files changed, 6 insertions(+), 7 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 67e4c0efd2..278d163803 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -1589,12 +1589,9 @@ void riscv_cpu_do_interrupt(CPUState *cs) target_ulong mtval2 = 0; if (cause == RISCV_EXCP_SEMIHOST) { - if (env->priv >= PRV_S) { - do_common_semihosting(cs); - env->pc += 4; - return; - } - cause = RISCV_EXCP_BREAKPOINT; + do_common_semihosting(cs); + env->pc += 4; + return; } if (!async) { diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/insn_trans/trans_privileged.c.inc index 46f96ad74d..3281408a87 100644 --- a/target/riscv/insn_trans/trans_privileged.c.inc +++ b/target/riscv/insn_trans/trans_privileged.c.inc @@ -52,7 +52,8 @@ static bool trans_ebreak(DisasContext *ctx, arg_ebreak *a) * that no exception will be raised when fetching them. */ - if ((pre_addr & TARGET_PAGE_MASK) == (post_addr & TARGET_PAGE_MASK)) { + if (semihosting_enabled(ctx->mem_idx < PRV_S) && + (pre_addr & TARGET_PAGE_MASK) == (post_addr & TARGET_PAGE_MASK)) { pre = opcode_at(&ctx->base, pre_addr); ebreak = opcode_at(&ctx->base, ebreak_addr); post = opcode_at(&ctx->base, post_addr); diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 8925a44c6e..db123da5ec 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -28,6 +28,7 @@ #include "exec/translator.h" #include "exec/log.h" +#include "semihosting/semihost.h" #include "instmap.h" #include "internals.h"