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target-arm: Handle UNDEF cases for Neon invalid modified-immediates

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For Neon "one register and a modified immediate value" forms, the
combination op=1 cmode=1111 is unallocated and should UNDEF.
All instructions of this form also UNDEF if Q == 1 and Vd<0> == 1.
We also add a comment on the only UNPREDICTABLE in this space.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
This commit is contained in:
Peter Maydell 2011-04-11 16:26:16 +01:00 committed by Aurelien Jarno
parent 2bc70834e8
commit 7d80fee5b9
1 changed files with 10 additions and 0 deletions
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10
target-arm/translate.c
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@ -5084,11 +5084,18 @@ static int disas_neon_data_insn(CPUState * env, DisasContext *s, uint32_t insn)
}
} else { /* (insn & 0x00380080) == 0 */
int invert;
if (q && (rd & 1)) {
return 1;
}
op = (insn >> 8) & 0xf;
/* One register and immediate. */
imm = (u << 7) | ((insn >> 12) & 0x70) | (insn & 0xf);
invert = (insn & (1 << 5)) != 0;
/* Note that op = 2,3,4,5,6,7,10,11,12,13 imm=0 is UNPREDICTABLE.
* We choose to not special-case this and will behave as if a
* valid constant encoding of 0 had been given.
*/
switch (op) {
case 0: case 1:
/* no-op */
@ -5120,6 +5127,9 @@ static int disas_neon_data_insn(CPUState * env, DisasContext *s, uint32_t insn)
imm = ~imm;
break;
case 15:
if (invert) {
return 1;
}
imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19)
| ((imm & 0x40) ? (0x1f << 25) : (1 << 30));
break;