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arm: add dummy A9-specific cp15 registers

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Add dummy register support for the cp15, CRn=c15 registers.

config_base_register and power_control_register currently
default to 0, but may have improved support after the QOM
CPU patches are finished.

Signed-off-by: Mark Langsdorf <mark.langsdorf@calxeda.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Mark Langsdorf 2012-01-05 15:49:06 +00:00 committed by Peter Maydell
parent 37064a8b6f
commit 7da362d016
3 changed files with 59 additions and 1 deletions
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6
target-arm/cpu.h
View File

@ -149,6 +149,10 @@ typedef struct CPUARMState {
uint32_t c15_i_max; /* Maximum D-cache dirty line index. */
uint32_t c15_i_min; /* Minimum D-cache dirty line index. */
uint32_t c15_threadid; /* TI debugger thread-ID. */
uint32_t c15_config_base_address; /* SCU base address. */
uint32_t c15_diagnostic; /* diagnostic register */
uint32_t c15_power_diagnostic;
uint32_t c15_power_control; /* power control */
} cp15;
struct {
@ -448,7 +452,7 @@ void cpu_arm_set_cp_io(CPUARMState *env, int cpnum,
#define cpu_signal_handler cpu_arm_signal_handler
#define cpu_list arm_cpu_list
#define CPU_SAVE_VERSION 4
#define CPU_SAVE_VERSION 5
/* MMU modes definitions */
#define MMU_MODE0_SUFFIX _kernel

48
target-arm/helper.c
View File

@ -1796,6 +1796,20 @@ void HELPER(set_cp15)(CPUState *env, uint32_t insn, uint32_t val)
goto bad_reg;
}
}
if (ARM_CPUID(env) == ARM_CPUID_CORTEXA9) {
switch (crm) {
case 0:
if ((op1 == 0) && (op2 == 0)) {
env->cp15.c15_power_control = val;
} else if ((op1 == 0) && (op2 == 1)) {
env->cp15.c15_diagnostic = val;
} else if ((op1 == 0) && (op2 == 2)) {
env->cp15.c15_power_diagnostic = val;
}
default:
break;
}
}
break;
}
return;
@ -2139,6 +2153,40 @@ uint32_t HELPER(get_cp15)(CPUState *env, uint32_t insn)
* 0x200 << ($rn & 0xfff), when MMU is off. */
goto bad_reg;
}
if (ARM_CPUID(env) == ARM_CPUID_CORTEXA9) {
switch (crm) {
case 0:
if ((op1 == 4) && (op2 == 0)) {
/* The config_base_address should hold the value of
* the peripheral base. ARM should get this from a CPU
* object property, but that support isn't available in
* December 2011. Default to 0 for now and board models
* that care can set it by a private hook */
return env->cp15.c15_config_base_address;
} else if ((op1 == 0) && (op2 == 0)) {
/* power_control should be set to maximum latency. Again,
default to 0 and set by private hook */
return env->cp15.c15_power_control;
} else if ((op1 == 0) && (op2 == 1)) {
return env->cp15.c15_diagnostic;
} else if ((op1 == 0) && (op2 == 2)) {
return env->cp15.c15_power_diagnostic;
}
break;
case 1: /* NEON Busy */
return 0;
case 5: /* tlb lockdown */
case 6:
case 7:
if ((op1 == 5) && (op2 == 2)) {
return 0;
}
break;
default:
break;
}
goto bad_reg;
}
return 0;
}
bad_reg:

6
target-arm/machine.c
View File

@ -56,6 +56,9 @@ void cpu_save(QEMUFile *f, void *opaque)
qemu_put_be32(f, env->cp15.c13_tls2);
qemu_put_be32(f, env->cp15.c13_tls3);
qemu_put_be32(f, env->cp15.c15_cpar);
qemu_put_be32(f, env->cp15.c15_power_control);
qemu_put_be32(f, env->cp15.c15_diagnostic);
qemu_put_be32(f, env->cp15.c15_power_diagnostic);
qemu_put_be32(f, env->features);
@ -170,6 +173,9 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id)
env->cp15.c13_tls2 = qemu_get_be32(f);
env->cp15.c13_tls3 = qemu_get_be32(f);
env->cp15.c15_cpar = qemu_get_be32(f);
env->cp15.c15_power_control = qemu_get_be32(f);
env->cp15.c15_diagnostic = qemu_get_be32(f);
env->cp15.c15_power_diagnostic = qemu_get_be32(f);
env->features = qemu_get_be32(f);