target/hexagon: make helper functions non-static
Make certain helper functions non-static, making them available outside genptr.c. These functions are required by code generated by the idef-parser. This commit also makes some functions in op_helper.c non-static in order to avoid having them marked as unused when using the idef-parser generated code. Signed-off-by: Alessandro Di Federico <ale@rev.ng> Signed-off-by: Paolo Montesel <babush@rev.ng> Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Taylor Simpson <tsimpson@quicinc.com> Message-Id: <20220923173831.227551-5-anjo@rev.ng>
This commit is contained in:
Paolo Montesel
Taylor Simpson
parent
d909808ec0
commit
7e8b3b395f
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@ -29,6 +29,13 @@
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#undef QEMU_GENERATE
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#include "gen_tcg.h"
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#include "gen_tcg_hvx.h"
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#include "genptr.h"
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TCGv gen_read_preg(TCGv pred, uint8_t num)
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{
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tcg_gen_mov_tl(pred, hex_pred[num]);
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return pred;
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}
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static inline void gen_log_predicated_reg_write(int rnum, TCGv val,
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uint32_t slot)
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@ -54,7 +61,7 @@ static inline void gen_log_predicated_reg_write(int rnum, TCGv val,
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tcg_temp_free(slot_mask);
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}
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static inline void gen_log_reg_write(int rnum, TCGv val)
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void gen_log_reg_write(int rnum, TCGv val)
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{
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tcg_gen_mov_tl(hex_new_value[rnum], val);
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if (HEX_DEBUG) {
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@ -116,7 +123,7 @@ static void gen_log_reg_write_pair(int rnum, TCGv_i64 val)
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}
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}
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static inline void gen_log_pred_write(DisasContext *ctx, int pnum, TCGv val)
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void gen_log_pred_write(DisasContext *ctx, int pnum, TCGv val)
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{
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TCGv base_val = tcg_temp_new();
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@ -274,7 +281,7 @@ static inline void gen_write_ctrl_reg_pair(DisasContext *ctx, int reg_num,
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}
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}
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static TCGv gen_get_byte(TCGv result, int N, TCGv src, bool sign)
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TCGv gen_get_byte(TCGv result, int N, TCGv src, bool sign)
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{
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if (sign) {
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tcg_gen_sextract_tl(result, src, N * 8, 8);
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@ -284,7 +291,7 @@ static TCGv gen_get_byte(TCGv result, int N, TCGv src, bool sign)
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return result;
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}
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static TCGv gen_get_byte_i64(TCGv result, int N, TCGv_i64 src, bool sign)
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TCGv gen_get_byte_i64(TCGv result, int N, TCGv_i64 src, bool sign)
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{
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TCGv_i64 res64 = tcg_temp_new_i64();
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if (sign) {
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@ -298,7 +305,7 @@ static TCGv gen_get_byte_i64(TCGv result, int N, TCGv_i64 src, bool sign)
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return result;
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}
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static inline TCGv gen_get_half(TCGv result, int N, TCGv src, bool sign)
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TCGv gen_get_half(TCGv result, int N, TCGv src, bool sign)
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{
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if (sign) {
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tcg_gen_sextract_tl(result, src, N * 16, 16);
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@ -308,12 +315,12 @@ static inline TCGv gen_get_half(TCGv result, int N, TCGv src, bool sign)
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return result;
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}
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static inline void gen_set_half(int N, TCGv result, TCGv src)
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void gen_set_half(int N, TCGv result, TCGv src)
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{
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tcg_gen_deposit_tl(result, result, src, N * 16, 16);
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}
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static inline void gen_set_half_i64(int N, TCGv_i64 result, TCGv src)
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void gen_set_half_i64(int N, TCGv_i64 result, TCGv src)
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{
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TCGv_i64 src64 = tcg_temp_new_i64();
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tcg_gen_extu_i32_i64(src64, src);
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@ -321,7 +328,7 @@ static inline void gen_set_half_i64(int N, TCGv_i64 result, TCGv src)
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tcg_temp_free_i64(src64);
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}
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static void gen_set_byte_i64(int N, TCGv_i64 result, TCGv src)
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void gen_set_byte_i64(int N, TCGv_i64 result, TCGv src)
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{
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TCGv_i64 src64 = tcg_temp_new_i64();
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tcg_gen_extu_i32_i64(src64, src);
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@ -396,60 +403,60 @@ static inline void gen_store_conditional8(DisasContext *ctx,
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tcg_gen_movi_tl(hex_llsc_addr, ~0);
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}
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static inline void gen_store32(TCGv vaddr, TCGv src, int width, uint32_t slot)
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void gen_store32(TCGv vaddr, TCGv src, int width, uint32_t slot)
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{
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tcg_gen_mov_tl(hex_store_addr[slot], vaddr);
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tcg_gen_movi_tl(hex_store_width[slot], width);
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tcg_gen_mov_tl(hex_store_val32[slot], src);
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}
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static inline void gen_store1(TCGv_env cpu_env, TCGv vaddr, TCGv src, uint32_t slot)
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void gen_store1(TCGv_env cpu_env, TCGv vaddr, TCGv src, uint32_t slot)
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{
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gen_store32(vaddr, src, 1, slot);
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}
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static inline void gen_store1i(TCGv_env cpu_env, TCGv vaddr, int32_t src, uint32_t slot)
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void gen_store1i(TCGv_env cpu_env, TCGv vaddr, int32_t src, uint32_t slot)
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{
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TCGv tmp = tcg_constant_tl(src);
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gen_store1(cpu_env, vaddr, tmp, slot);
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}
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static inline void gen_store2(TCGv_env cpu_env, TCGv vaddr, TCGv src, uint32_t slot)
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void gen_store2(TCGv_env cpu_env, TCGv vaddr, TCGv src, uint32_t slot)
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{
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gen_store32(vaddr, src, 2, slot);
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}
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static inline void gen_store2i(TCGv_env cpu_env, TCGv vaddr, int32_t src, uint32_t slot)
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void gen_store2i(TCGv_env cpu_env, TCGv vaddr, int32_t src, uint32_t slot)
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{
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TCGv tmp = tcg_constant_tl(src);
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gen_store2(cpu_env, vaddr, tmp, slot);
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}
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static inline void gen_store4(TCGv_env cpu_env, TCGv vaddr, TCGv src, uint32_t slot)
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void gen_store4(TCGv_env cpu_env, TCGv vaddr, TCGv src, uint32_t slot)
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{
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gen_store32(vaddr, src, 4, slot);
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}
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static inline void gen_store4i(TCGv_env cpu_env, TCGv vaddr, int32_t src, uint32_t slot)
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void gen_store4i(TCGv_env cpu_env, TCGv vaddr, int32_t src, uint32_t slot)
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{
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TCGv tmp = tcg_constant_tl(src);
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gen_store4(cpu_env, vaddr, tmp, slot);
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}
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static inline void gen_store8(TCGv_env cpu_env, TCGv vaddr, TCGv_i64 src, uint32_t slot)
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void gen_store8(TCGv_env cpu_env, TCGv vaddr, TCGv_i64 src, uint32_t slot)
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{
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tcg_gen_mov_tl(hex_store_addr[slot], vaddr);
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tcg_gen_movi_tl(hex_store_width[slot], 8);
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tcg_gen_mov_i64(hex_store_val64[slot], src);
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}
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static inline void gen_store8i(TCGv_env cpu_env, TCGv vaddr, int64_t src, uint32_t slot)
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void gen_store8i(TCGv_env cpu_env, TCGv vaddr, int64_t src, uint32_t slot)
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{
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TCGv_i64 tmp = tcg_constant_i64(src);
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gen_store8(cpu_env, vaddr, tmp, slot);
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}
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static TCGv gen_8bitsof(TCGv result, TCGv value)
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TCGv gen_8bitsof(TCGv result, TCGv value)
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{
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TCGv zero = tcg_constant_tl(0);
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TCGv ones = tcg_constant_tl(0xff);
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@ -1014,7 +1021,7 @@ static void vec_to_qvec(size_t size, intptr_t dstoff, intptr_t srcoff)
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tcg_temp_free_i64(mask);
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}
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static void probe_noshuf_load(TCGv va, int s, int mi)
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void probe_noshuf_load(TCGv va, int s, int mi)
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{
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TCGv size = tcg_constant_tl(s);
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TCGv mem_idx = tcg_constant_tl(mi);
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@ -19,7 +19,30 @@
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#define HEXAGON_GENPTR_H
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#include "insn.h"
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#include "tcg/tcg.h"
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#include "translate.h"
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extern const SemanticInsn opcode_genptr[];
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void gen_store32(TCGv vaddr, TCGv src, int width, uint32_t slot);
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void gen_store1(TCGv_env cpu_env, TCGv vaddr, TCGv src, uint32_t slot);
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void gen_store2(TCGv_env cpu_env, TCGv vaddr, TCGv src, uint32_t slot);
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void gen_store4(TCGv_env cpu_env, TCGv vaddr, TCGv src, uint32_t slot);
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void gen_store8(TCGv_env cpu_env, TCGv vaddr, TCGv_i64 src, uint32_t slot);
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void gen_store1i(TCGv_env cpu_env, TCGv vaddr, int32_t src, uint32_t slot);
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void gen_store2i(TCGv_env cpu_env, TCGv vaddr, int32_t src, uint32_t slot);
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void gen_store4i(TCGv_env cpu_env, TCGv vaddr, int32_t src, uint32_t slot);
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void gen_store8i(TCGv_env cpu_env, TCGv vaddr, int64_t src, uint32_t slot);
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TCGv gen_read_preg(TCGv pred, uint8_t num);
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void gen_log_reg_write(int rnum, TCGv val);
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void gen_log_pred_write(DisasContext *ctx, int pnum, TCGv val);
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TCGv gen_8bitsof(TCGv result, TCGv value);
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void gen_set_byte_i64(int N, TCGv_i64 result, TCGv src);
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TCGv gen_get_byte(TCGv result, int N, TCGv src, bool sign);
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TCGv gen_get_byte_i64(TCGv result, int N, TCGv_i64 src, bool sign);
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TCGv gen_get_half(TCGv result, int N, TCGv src, bool sign);
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void gen_set_half(int N, TCGv result, TCGv src);
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void gen_set_half_i64(int N, TCGv_i64 result, TCGv src);
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void probe_noshuf_load(TCGv va, int s, int mi);
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#endif
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@ -29,6 +29,7 @@
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#include "fma_emu.h"
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#include "mmvec/mmvec.h"
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#include "mmvec/macros.h"
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#include "op_helper.h"
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#define SF_BIAS 127
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#define SF_MANTBITS 23
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@ -50,8 +51,8 @@ G_NORETURN void HELPER(raise_exception)(CPUHexagonState *env, uint32_t excp)
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do_raise_exception_err(env, excp, 0);
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}
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static void log_reg_write(CPUHexagonState *env, int rnum,
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target_ulong val, uint32_t slot)
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void log_reg_write(CPUHexagonState *env, int rnum,
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target_ulong val, uint32_t slot)
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{
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HEX_DEBUG_LOG("log_reg_write[%d] = " TARGET_FMT_ld " (0x" TARGET_FMT_lx ")",
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rnum, val, val);
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@ -82,8 +83,8 @@ static void log_pred_write(CPUHexagonState *env, int pnum, target_ulong val)
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}
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}
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static void log_store32(CPUHexagonState *env, target_ulong addr,
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target_ulong val, int width, int slot)
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void log_store32(CPUHexagonState *env, target_ulong addr,
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target_ulong val, int width, int slot)
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{
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HEX_DEBUG_LOG("log_store%d(0x" TARGET_FMT_lx
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", %" PRId32 " [0x08%" PRIx32 "])\n",
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@ -93,8 +94,8 @@ static void log_store32(CPUHexagonState *env, target_ulong addr,
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env->mem_log_stores[slot].data32 = val;
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}
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static void log_store64(CPUHexagonState *env, target_ulong addr,
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int64_t val, int width, int slot)
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void log_store64(CPUHexagonState *env, target_ulong addr,
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int64_t val, int width, int slot)
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{
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HEX_DEBUG_LOG("log_store%d(0x" TARGET_FMT_lx
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", %" PRId64 " [0x016%" PRIx64 "])\n",
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@ -104,7 +105,7 @@ static void log_store64(CPUHexagonState *env, target_ulong addr,
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env->mem_log_stores[slot].data64 = val;
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}
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static void write_new_pc(CPUHexagonState *env, bool pkt_has_multi_cof,
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void write_new_pc(CPUHexagonState *env, bool pkt_has_multi_cof,
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target_ulong addr)
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{
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HEX_DEBUG_LOG("write_new_pc(0x" TARGET_FMT_lx ")\n", addr);
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@ -541,32 +542,28 @@ static void check_noshuf(CPUHexagonState *env, uint32_t slot,
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}
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}
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static uint8_t mem_load1(CPUHexagonState *env, uint32_t slot,
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target_ulong vaddr)
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uint8_t mem_load1(CPUHexagonState *env, uint32_t slot, target_ulong vaddr)
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{
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uintptr_t ra = GETPC();
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check_noshuf(env, slot, vaddr, 1);
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return cpu_ldub_data_ra(env, vaddr, ra);
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}
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static uint16_t mem_load2(CPUHexagonState *env, uint32_t slot,
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target_ulong vaddr)
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uint16_t mem_load2(CPUHexagonState *env, uint32_t slot, target_ulong vaddr)
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{
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uintptr_t ra = GETPC();
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check_noshuf(env, slot, vaddr, 2);
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return cpu_lduw_data_ra(env, vaddr, ra);
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}
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static uint32_t mem_load4(CPUHexagonState *env, uint32_t slot,
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target_ulong vaddr)
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uint32_t mem_load4(CPUHexagonState *env, uint32_t slot, target_ulong vaddr)
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{
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uintptr_t ra = GETPC();
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check_noshuf(env, slot, vaddr, 4);
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return cpu_ldl_data_ra(env, vaddr, ra);
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}
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static uint64_t mem_load8(CPUHexagonState *env, uint32_t slot,
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target_ulong vaddr)
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uint64_t mem_load8(CPUHexagonState *env, uint32_t slot, target_ulong vaddr)
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{
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uintptr_t ra = GETPC();
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check_noshuf(env, slot, vaddr, 8);
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@ -1471,7 +1468,7 @@ void HELPER(vwhist128qm)(CPUHexagonState *env, int32_t uiV)
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}
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}
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static void cancel_slot(CPUHexagonState *env, uint32_t slot)
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void cancel_slot(CPUHexagonState *env, uint32_t slot)
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{
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HEX_DEBUG_LOG("Slot %d cancelled\n", slot);
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env->slot_cancelled |= (1 << slot);
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@ -0,0 +1,37 @@
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/*
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* Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef HEXAGON_OP_HELPER_H
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#define HEXAGON_OP_HELPER_H
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/* Misc functions */
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void cancel_slot(CPUHexagonState *env, uint32_t slot);
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void write_new_pc(CPUHexagonState *env, bool pkt_has_multi_cof, target_ulong addr);
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uint8_t mem_load1(CPUHexagonState *env, uint32_t slot, target_ulong vaddr);
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uint16_t mem_load2(CPUHexagonState *env, uint32_t slot, target_ulong vaddr);
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uint32_t mem_load4(CPUHexagonState *env, uint32_t slot, target_ulong vaddr);
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uint64_t mem_load8(CPUHexagonState *env, uint32_t slot, target_ulong vaddr);
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void log_reg_write(CPUHexagonState *env, int rnum,
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target_ulong val, uint32_t slot);
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void log_store64(CPUHexagonState *env, target_ulong addr,
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int64_t val, int width, int slot);
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void log_store32(CPUHexagonState *env, target_ulong addr,
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target_ulong val, int width, int slot);
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#endif
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