target/riscv: gdbstub: Drop the vector CSRs in riscv-vector.xml
It's worth noting that the vector CSR predicate() has a similar
run-time check logic to the FPU CSR. With the previous patch our
gdbstub can correctly report these vector CSRs via the CSR xml.
Commit 719d3561b2
("target/riscv: gdb: support vector registers for rv64 & rv32")
inserted these vector CSRs in an ad-hoc, non-standard way in the
riscv-vector.xml. Now we can treat these CSRs no different from
other CSRs.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Message-ID: <20230228104035.1879882-13-bmeng@tinylab.org>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
This commit is contained in:
parent
a1f0083c6e
commit
7eac8f4191
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@ -127,40 +127,6 @@ static int riscv_gdb_set_fpu(CPURISCVState *env, uint8_t *mem_buf, int n)
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return 0;
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}
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/*
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* Convert register index number passed by GDB to the correspond
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* vector CSR number. Vector CSRs are defined after vector registers
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* in dynamic generated riscv-vector.xml, thus the starting register index
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* of vector CSRs is 32.
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* Return 0 if register index number is out of range.
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*/
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static int riscv_gdb_vector_csrno(int num_regs)
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{
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/*
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* The order of vector CSRs in the switch case
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* should match with the order defined in csr_ops[].
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*/
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switch (num_regs) {
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case 32:
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return CSR_VSTART;
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case 33:
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return CSR_VXSAT;
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case 34:
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return CSR_VXRM;
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case 35:
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return CSR_VCSR;
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case 36:
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return CSR_VL;
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case 37:
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return CSR_VTYPE;
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case 38:
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return CSR_VLENB;
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default:
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/* Unknown register. */
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return 0;
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}
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}
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static int riscv_gdb_get_vector(CPURISCVState *env, GByteArray *buf, int n)
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{
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uint16_t vlenb = env_archcpu(env)->cfg.vlen >> 3;
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@ -174,19 +140,6 @@ static int riscv_gdb_get_vector(CPURISCVState *env, GByteArray *buf, int n)
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return cnt;
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}
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int csrno = riscv_gdb_vector_csrno(n);
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if (!csrno) {
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return 0;
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}
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target_ulong val = 0;
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int result = riscv_csrrw_debug(env, csrno, &val, 0, 0);
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if (result == RISCV_EXCP_NONE) {
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return gdb_get_regl(buf, val);
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}
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return 0;
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}
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@ -201,19 +154,6 @@ static int riscv_gdb_set_vector(CPURISCVState *env, uint8_t *mem_buf, int n)
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return vlenb;
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}
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int csrno = riscv_gdb_vector_csrno(n);
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if (!csrno) {
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return 0;
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}
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target_ulong val = ldtul_p(mem_buf);
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int result = riscv_csrrw_debug(env, csrno, NULL, val, -1);
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if (result == RISCV_EXCP_NONE) {
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return sizeof(target_ulong);
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}
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return 0;
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}
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@ -361,21 +301,6 @@ static int ricsv_gen_dynamic_vector_xml(CPUState *cs, int base_reg)
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num_regs++;
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}
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/* Define vector CSRs */
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const char *vector_csrs[7] = {
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"vstart", "vxsat", "vxrm", "vcsr",
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"vl", "vtype", "vlenb"
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};
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for (i = 0; i < 7; i++) {
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g_string_append_printf(s,
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"<reg name=\"%s\" bitsize=\"%d\""
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" regnum=\"%d\" group=\"vector\""
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" type=\"int\"/>",
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vector_csrs[i], TARGET_LONG_BITS, base_reg++);
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num_regs++;
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}
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g_string_append_printf(s, "</feature>");
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cpu->dyn_vreg_xml = g_string_free(s, false);
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