i386: Add new CPU model SapphireRapids
The new CPU model mostly inherits features from Icelake-Server, while adding new features: - AMX (Advance Matrix eXtensions) - Bus Lock Debug Exception and new instructions: - AVX VNNI (Vector Neural Network Instruction): - VPDPBUS: Multiply and Add Unsigned and Signed Bytes - VPDPBUSDS: Multiply and Add Unsigned and Signed Bytes with Saturation - VPDPWSSD: Multiply and Add Signed Word Integers - VPDPWSSDS: Multiply and Add Signed Integers with Saturation - FP16: Replicates existing AVX512 computational SP (FP32) instructions using FP16 instead of FP32 for ~2X performance gain - SERIALIZE: Provide software with a simple way to force the processor to complete all modifications, faster, allowed in all privilege levels and not causing an unconditional VM exit - TSX Suspend Load Address Tracking: Allows programmers to choose which memory accesses do not need to be tracked in the TSX read set - AVX512_BF16: Vector Neural Network Instructions supporting BFLOAT16 inputs and conversion instructions from IEEE single precision - fast zero-length MOVSB (KVM doesn't support yet) - fast short STOSB (KVM doesn't support yet) - fast short CMPSB, SCASB (KVM doesn't support yet) Features that may be added in future versions: - CET (virtualization support hasn't been merged) Signed-off-by: Wang, Lei <lei4.wang@intel.com> Reviewed-by: Robert Hoo <robert.hu@linux.intel.com> Message-Id: <20220812055751.14553-1-lei4.wang@intel.com> Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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@ -3468,6 +3468,135 @@ static const X86CPUDefinition builtin_x86_defs[] = {
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{ /* end of list */ }
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}
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},
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{
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.name = "SapphireRapids",
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.level = 0x20,
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.vendor = CPUID_VENDOR_INTEL,
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.family = 6,
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.model = 143,
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.stepping = 4,
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/*
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* please keep the ascending order so that we can have a clear view of
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* bit position of each feature.
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*/
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.features[FEAT_1_EDX] =
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CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC |
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CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC |
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CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV |
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CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FXSR |
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CPUID_SSE | CPUID_SSE2,
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.features[FEAT_1_ECX] =
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CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 |
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CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID | CPUID_EXT_SSE41 |
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CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE |
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CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AES |
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CPUID_EXT_XSAVE | CPUID_EXT_AVX | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
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.features[FEAT_8000_0001_EDX] =
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CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB |
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CPUID_EXT2_RDTSCP | CPUID_EXT2_LM,
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.features[FEAT_8000_0001_ECX] =
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CPUID_EXT3_LAHF_LM | CPUID_EXT3_ABM | CPUID_EXT3_3DNOWPREFETCH,
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.features[FEAT_8000_0008_EBX] =
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CPUID_8000_0008_EBX_WBNOINVD,
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.features[FEAT_7_0_EBX] =
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CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_HLE |
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CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 |
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CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_RTM |
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CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
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CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP |
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CPUID_7_0_EBX_AVX512IFMA | CPUID_7_0_EBX_CLFLUSHOPT |
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CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_AVX512CD | CPUID_7_0_EBX_SHA_NI |
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CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512VL,
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.features[FEAT_7_0_ECX] =
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CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_PKU |
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CPUID_7_0_ECX_AVX512_VBMI2 | CPUID_7_0_ECX_GFNI |
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CPUID_7_0_ECX_VAES | CPUID_7_0_ECX_VPCLMULQDQ |
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CPUID_7_0_ECX_AVX512VNNI | CPUID_7_0_ECX_AVX512BITALG |
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CPUID_7_0_ECX_AVX512_VPOPCNTDQ | CPUID_7_0_ECX_LA57 |
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CPUID_7_0_ECX_RDPID | CPUID_7_0_ECX_BUS_LOCK_DETECT,
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.features[FEAT_7_0_EDX] =
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CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_SERIALIZE |
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CPUID_7_0_EDX_TSX_LDTRK | CPUID_7_0_EDX_AMX_BF16 |
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CPUID_7_0_EDX_AVX512_FP16 | CPUID_7_0_EDX_AMX_TILE |
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CPUID_7_0_EDX_AMX_INT8 | CPUID_7_0_EDX_SPEC_CTRL |
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CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD,
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.features[FEAT_ARCH_CAPABILITIES] =
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MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL |
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MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO |
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MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO,
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.features[FEAT_XSAVE] =
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CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
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CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES | CPUID_D_1_EAX_XFD,
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.features[FEAT_6_EAX] =
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CPUID_6_EAX_ARAT,
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.features[FEAT_7_1_EAX] =
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CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_AVX512_BF16 |
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CPUID_7_1_EAX_FZRM | CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_FSRC,
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.features[FEAT_VMX_BASIC] =
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MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS,
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.features[FEAT_VMX_ENTRY_CTLS] =
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VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE |
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VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL |
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VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER,
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.features[FEAT_VMX_EPT_VPID_CAPS] =
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MSR_VMX_EPT_EXECONLY |
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MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_PAGE_WALK_LENGTH_5 |
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MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB |
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MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS |
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MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
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MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
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MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT |
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MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
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MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS,
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.features[FEAT_VMX_EXIT_CTLS] =
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VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
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VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
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VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT |
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VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
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VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
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.features[FEAT_VMX_MISC] =
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MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT |
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MSR_VMX_MISC_VMWRITE_VMEXIT,
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.features[FEAT_VMX_PINBASED_CTLS] =
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VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING |
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VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIMER |
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VMX_PIN_BASED_POSTED_INTR,
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.features[FEAT_VMX_PROCBASED_CTLS] =
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VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
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VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
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VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
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VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
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VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
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VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
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VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_VIRTUAL_NMI_PENDING |
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VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING |
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VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_TRAP_FLAG |
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VMX_CPU_BASED_USE_MSR_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING |
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VMX_CPU_BASED_PAUSE_EXITING |
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VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
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.features[FEAT_VMX_SECONDARY_CTLS] =
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VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
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VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC |
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VMX_SECONDARY_EXEC_RDTSCP |
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VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
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VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_WBINVD_EXITING |
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VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
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VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
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VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
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VMX_SECONDARY_EXEC_RDRAND_EXITING |
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VMX_SECONDARY_EXEC_ENABLE_INVPCID |
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VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
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VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML |
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VMX_SECONDARY_EXEC_XSAVES,
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.features[FEAT_VMX_VMFUNC] =
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MSR_VMX_VMFUNC_EPT_SWITCHING,
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.xlevel = 0x80000008,
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.model_id = "Intel Xeon Processor (SapphireRapids)",
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.versions = (X86CPUVersionDefinition[]) {
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{ .version = 1 },
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{ /* end of list */ },
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},
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},
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{
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.name = "Denverton",
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.level = 21,
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@ -5623,7 +5752,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
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break;
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}
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case 0x1D: {
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/* AMX TILE */
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/* AMX TILE, for now hardcoded for Sapphire Rapids*/
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*eax = 0;
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*ebx = 0;
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*ecx = 0;
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@ -5644,7 +5773,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
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break;
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}
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case 0x1E: {
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/* AMX TMUL */
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/* AMX TMUL, for now hardcoded for Sapphire Rapids */
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*eax = 0;
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*ebx = 0;
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*ecx = 0;
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@ -881,10 +881,14 @@ uint64_t x86_cpu_get_supported_feature_word(FeatureWord w,
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#define CPUID_7_0_EDX_TSX_LDTRK (1U << 16)
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/* Architectural LBRs */
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#define CPUID_7_0_EDX_ARCH_LBR (1U << 19)
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/* AMX_BF16 instruction */
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#define CPUID_7_0_EDX_AMX_BF16 (1U << 22)
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/* AVX512_FP16 instruction */
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#define CPUID_7_0_EDX_AVX512_FP16 (1U << 23)
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/* AMX tile (two-dimensional register) */
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#define CPUID_7_0_EDX_AMX_TILE (1U << 24)
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/* AMX_INT8 instruction */
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#define CPUID_7_0_EDX_AMX_INT8 (1U << 25)
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/* Speculation Control */
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#define CPUID_7_0_EDX_SPEC_CTRL (1U << 26)
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/* Single Thread Indirect Branch Predictors */
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