hw/block/nvme: add PMR RDS/WDS support
Add support for the PMRMSCL and PMRMSCU MMIO registers. This allows adding RDS/WDS support for PMR as well. Reviewed-by: Keith Busch <kbusch@kernel.org> Signed-off-by: Naveen Nagar <naveen.n1@samsung.com> Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
This commit is contained in:
parent
75c3c9de96
commit
7ec9f2eef9
122
hw/block/nvme.c
122
hw/block/nvme.c
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@ -273,6 +273,24 @@ static inline void *nvme_addr_to_cmb(NvmeCtrl *n, hwaddr addr)
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return &n->cmbuf[addr - n->ctrl_mem.addr];
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return &n->cmbuf[addr - n->ctrl_mem.addr];
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}
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}
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static bool nvme_addr_is_pmr(NvmeCtrl *n, hwaddr addr)
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{
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hwaddr hi;
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if (!n->pmr.cmse) {
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return false;
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}
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hi = n->pmr.cba + int128_get64(n->pmr.dev->mr.size);
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return addr >= n->pmr.cba && addr < hi;
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}
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static inline void *nvme_addr_to_pmr(NvmeCtrl *n, hwaddr addr)
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{
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return memory_region_get_ram_ptr(&n->pmr.dev->mr) + (addr - n->pmr.cba);
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}
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static int nvme_addr_read(NvmeCtrl *n, hwaddr addr, void *buf, int size)
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static int nvme_addr_read(NvmeCtrl *n, hwaddr addr, void *buf, int size)
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{
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{
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hwaddr hi = addr + size - 1;
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hwaddr hi = addr + size - 1;
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@ -285,6 +303,11 @@ static int nvme_addr_read(NvmeCtrl *n, hwaddr addr, void *buf, int size)
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return 0;
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return 0;
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}
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}
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if (nvme_addr_is_pmr(n, addr) && nvme_addr_is_pmr(n, hi)) {
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memcpy(buf, nvme_addr_to_pmr(n, addr), size);
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return 0;
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}
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return pci_dma_read(&n->parent_obj, addr, buf, size);
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return pci_dma_read(&n->parent_obj, addr, buf, size);
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}
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}
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@ -406,9 +429,27 @@ static uint16_t nvme_map_addr_cmb(NvmeCtrl *n, QEMUIOVector *iov, hwaddr addr,
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return NVME_SUCCESS;
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return NVME_SUCCESS;
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}
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}
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static uint16_t nvme_map_addr_pmr(NvmeCtrl *n, QEMUIOVector *iov, hwaddr addr,
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size_t len)
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{
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if (!len) {
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return NVME_SUCCESS;
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}
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if (!nvme_addr_is_pmr(n, addr) || !nvme_addr_is_pmr(n, addr + len - 1)) {
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return NVME_DATA_TRAS_ERROR;
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}
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qemu_iovec_add(iov, nvme_addr_to_pmr(n, addr), len);
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return NVME_SUCCESS;
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}
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static uint16_t nvme_map_addr(NvmeCtrl *n, QEMUSGList *qsg, QEMUIOVector *iov,
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static uint16_t nvme_map_addr(NvmeCtrl *n, QEMUSGList *qsg, QEMUIOVector *iov,
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hwaddr addr, size_t len)
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hwaddr addr, size_t len)
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{
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{
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bool cmb = false, pmr = false;
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if (!len) {
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if (!len) {
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return NVME_SUCCESS;
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return NVME_SUCCESS;
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}
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}
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@ -416,6 +457,12 @@ static uint16_t nvme_map_addr(NvmeCtrl *n, QEMUSGList *qsg, QEMUIOVector *iov,
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trace_pci_nvme_map_addr(addr, len);
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trace_pci_nvme_map_addr(addr, len);
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if (nvme_addr_is_cmb(n, addr)) {
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if (nvme_addr_is_cmb(n, addr)) {
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cmb = true;
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} else if (nvme_addr_is_pmr(n, addr)) {
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pmr = true;
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}
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if (cmb || pmr) {
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if (qsg && qsg->sg) {
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if (qsg && qsg->sg) {
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return NVME_INVALID_USE_OF_CMB | NVME_DNR;
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return NVME_INVALID_USE_OF_CMB | NVME_DNR;
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}
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}
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@ -426,7 +473,11 @@ static uint16_t nvme_map_addr(NvmeCtrl *n, QEMUSGList *qsg, QEMUIOVector *iov,
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qemu_iovec_init(iov, 1);
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qemu_iovec_init(iov, 1);
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}
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}
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return nvme_map_addr_cmb(n, iov, addr, len);
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if (cmb) {
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return nvme_map_addr_cmb(n, iov, addr, len);
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} else {
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return nvme_map_addr_pmr(n, iov, addr, len);
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}
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}
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}
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if (iov && iov->iov) {
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if (iov && iov->iov) {
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@ -459,7 +510,7 @@ static uint16_t nvme_map_prp(NvmeCtrl *n, uint64_t prp1, uint64_t prp2,
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trace_pci_nvme_map_prp(trans_len, len, prp1, prp2, num_prps);
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trace_pci_nvme_map_prp(trans_len, len, prp1, prp2, num_prps);
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if (nvme_addr_is_cmb(n, prp1)) {
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if (nvme_addr_is_cmb(n, prp1) || (nvme_addr_is_pmr(n, prp1))) {
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qemu_iovec_init(iov, num_prps);
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qemu_iovec_init(iov, num_prps);
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} else {
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} else {
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pci_dma_sglist_init(qsg, &n->parent_obj, num_prps);
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pci_dma_sglist_init(qsg, &n->parent_obj, num_prps);
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@ -3561,8 +3612,8 @@ static void nvme_ctrl_shutdown(NvmeCtrl *n)
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NvmeNamespace *ns;
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NvmeNamespace *ns;
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int i;
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int i;
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if (n->pmrdev) {
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if (n->pmr.dev) {
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memory_region_msync(&n->pmrdev->mr, 0, n->pmrdev->size);
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memory_region_msync(&n->pmr.dev->mr, 0, n->pmr.dev->size);
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}
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}
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for (i = 1; i <= n->num_namespaces; i++) {
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for (i = 1; i <= n->num_namespaces; i++) {
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@ -3851,11 +3902,12 @@ static void nvme_write_bar(NvmeCtrl *n, hwaddr offset, uint64_t data,
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case 0xE04: /* PMRCTL */
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case 0xE04: /* PMRCTL */
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n->bar.pmrctl = data;
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n->bar.pmrctl = data;
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if (NVME_PMRCTL_EN(data)) {
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if (NVME_PMRCTL_EN(data)) {
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memory_region_set_enabled(&n->pmrdev->mr, true);
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memory_region_set_enabled(&n->pmr.dev->mr, true);
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n->bar.pmrsts = 0;
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n->bar.pmrsts = 0;
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} else {
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} else {
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memory_region_set_enabled(&n->pmrdev->mr, false);
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memory_region_set_enabled(&n->pmr.dev->mr, false);
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NVME_PMRSTS_SET_NRDY(n->bar.pmrsts, 1);
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NVME_PMRSTS_SET_NRDY(n->bar.pmrsts, 1);
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n->pmr.cmse = false;
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}
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}
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return;
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return;
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case 0xE08: /* PMRSTS */
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case 0xE08: /* PMRSTS */
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@ -3870,8 +3922,33 @@ static void nvme_write_bar(NvmeCtrl *n, hwaddr offset, uint64_t data,
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NVME_GUEST_ERR(pci_nvme_ub_mmiowr_pmrswtp_readonly,
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NVME_GUEST_ERR(pci_nvme_ub_mmiowr_pmrswtp_readonly,
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"invalid write to PMRSWTP register, ignored");
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"invalid write to PMRSWTP register, ignored");
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return;
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return;
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case 0xE14: /* TODO PMRMSC */
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case 0xE14: /* PMRMSCL */
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break;
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if (!NVME_CAP_PMRS(n->bar.cap)) {
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return;
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}
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n->bar.pmrmsc = (n->bar.pmrmsc & ~0xffffffff) | (data & 0xffffffff);
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n->pmr.cmse = false;
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if (NVME_PMRMSC_CMSE(n->bar.pmrmsc)) {
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hwaddr cba = NVME_PMRMSC_CBA(n->bar.pmrmsc) << PMRMSC_CBA_SHIFT;
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if (cba + int128_get64(n->pmr.dev->mr.size) < cba) {
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NVME_PMRSTS_SET_CBAI(n->bar.pmrsts, 1);
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return;
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}
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n->pmr.cmse = true;
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n->pmr.cba = cba;
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}
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return;
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case 0xE18: /* PMRMSCU */
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if (!NVME_CAP_PMRS(n->bar.cap)) {
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return;
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}
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n->bar.pmrmsc = (n->bar.pmrmsc & 0xffffffff) | (data << 32);
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return;
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default:
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default:
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NVME_GUEST_ERR(pci_nvme_ub_mmiowr_invalid,
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NVME_GUEST_ERR(pci_nvme_ub_mmiowr_invalid,
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"invalid MMIO write,"
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"invalid MMIO write,"
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@ -3909,7 +3986,7 @@ static uint64_t nvme_mmio_read(void *opaque, hwaddr addr, unsigned size)
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*/
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*/
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if (addr == 0xE08 &&
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if (addr == 0xE08 &&
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(NVME_PMRCAP_PMRWBM(n->bar.pmrcap) & 0x02)) {
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(NVME_PMRCAP_PMRWBM(n->bar.pmrcap) & 0x02)) {
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memory_region_msync(&n->pmrdev->mr, 0, n->pmrdev->size);
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memory_region_msync(&n->pmr.dev->mr, 0, n->pmr.dev->size);
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}
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}
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memcpy(&val, ptr + addr, size);
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memcpy(&val, ptr + addr, size);
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} else {
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} else {
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@ -4128,19 +4205,19 @@ static void nvme_check_constraints(NvmeCtrl *n, Error **errp)
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return;
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return;
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}
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}
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if (n->pmrdev) {
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if (n->pmr.dev) {
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if (host_memory_backend_is_mapped(n->pmrdev)) {
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if (host_memory_backend_is_mapped(n->pmr.dev)) {
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error_setg(errp, "can't use already busy memdev: %s",
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error_setg(errp, "can't use already busy memdev: %s",
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object_get_canonical_path_component(OBJECT(n->pmrdev)));
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object_get_canonical_path_component(OBJECT(n->pmr.dev)));
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return;
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return;
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}
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}
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if (!is_power_of_2(n->pmrdev->size)) {
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if (!is_power_of_2(n->pmr.dev->size)) {
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error_setg(errp, "pmr backend size needs to be power of 2 in size");
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error_setg(errp, "pmr backend size needs to be power of 2 in size");
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return;
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return;
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}
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}
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host_memory_backend_set_mapped(n->pmrdev, true);
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host_memory_backend_set_mapped(n->pmr.dev, true);
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}
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}
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if (n->params.zasl_bs) {
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if (n->params.zasl_bs) {
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@ -4225,16 +4302,19 @@ static void nvme_init_cmb(NvmeCtrl *n, PCIDevice *pci_dev)
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static void nvme_init_pmr(NvmeCtrl *n, PCIDevice *pci_dev)
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static void nvme_init_pmr(NvmeCtrl *n, PCIDevice *pci_dev)
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{
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{
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NVME_PMRCAP_SET_RDS(n->bar.pmrcap, 1);
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NVME_PMRCAP_SET_WDS(n->bar.pmrcap, 1);
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NVME_PMRCAP_SET_BIR(n->bar.pmrcap, NVME_PMR_BIR);
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NVME_PMRCAP_SET_BIR(n->bar.pmrcap, NVME_PMR_BIR);
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/* Turn on bit 1 support */
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/* Turn on bit 1 support */
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NVME_PMRCAP_SET_PMRWBM(n->bar.pmrcap, 0x02);
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NVME_PMRCAP_SET_PMRWBM(n->bar.pmrcap, 0x02);
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NVME_PMRCAP_SET_CMSS(n->bar.pmrcap, 1);
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pci_register_bar(pci_dev, NVME_PMRCAP_BIR(n->bar.pmrcap),
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pci_register_bar(pci_dev, NVME_PMRCAP_BIR(n->bar.pmrcap),
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PCI_BASE_ADDRESS_SPACE_MEMORY |
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PCI_BASE_ADDRESS_SPACE_MEMORY |
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PCI_BASE_ADDRESS_MEM_TYPE_64 |
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PCI_BASE_ADDRESS_MEM_TYPE_64 |
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PCI_BASE_ADDRESS_MEM_PREFETCH, &n->pmrdev->mr);
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PCI_BASE_ADDRESS_MEM_PREFETCH, &n->pmr.dev->mr);
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memory_region_set_enabled(&n->pmrdev->mr, false);
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memory_region_set_enabled(&n->pmr.dev->mr, false);
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}
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}
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static int nvme_init_pci(NvmeCtrl *n, PCIDevice *pci_dev, Error **errp)
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static int nvme_init_pci(NvmeCtrl *n, PCIDevice *pci_dev, Error **errp)
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@ -4295,7 +4375,7 @@ static int nvme_init_pci(NvmeCtrl *n, PCIDevice *pci_dev, Error **errp)
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nvme_init_cmb(n, pci_dev);
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nvme_init_cmb(n, pci_dev);
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}
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}
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if (n->pmrdev) {
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if (n->pmr.dev) {
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nvme_init_pmr(n, pci_dev);
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nvme_init_pmr(n, pci_dev);
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}
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}
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@ -4368,7 +4448,7 @@ static void nvme_init_ctrl(NvmeCtrl *n, PCIDevice *pci_dev)
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NVME_CAP_SET_CSS(n->bar.cap, NVME_CAP_CSS_ADMIN_ONLY);
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NVME_CAP_SET_CSS(n->bar.cap, NVME_CAP_CSS_ADMIN_ONLY);
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NVME_CAP_SET_MPSMAX(n->bar.cap, 4);
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NVME_CAP_SET_MPSMAX(n->bar.cap, 4);
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NVME_CAP_SET_CMBS(n->bar.cap, n->params.cmb_size_mb ? 1 : 0);
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NVME_CAP_SET_CMBS(n->bar.cap, n->params.cmb_size_mb ? 1 : 0);
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NVME_CAP_SET_PMRS(n->bar.cap, n->pmrdev ? 1 : 0);
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NVME_CAP_SET_PMRS(n->bar.cap, n->pmr.dev ? 1 : 0);
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n->bar.vs = NVME_SPEC_VER;
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n->bar.vs = NVME_SPEC_VER;
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n->bar.intmc = n->bar.intms = 0;
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n->bar.intmc = n->bar.intms = 0;
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@ -4432,15 +4512,15 @@ static void nvme_exit(PCIDevice *pci_dev)
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g_free(n->cmbuf);
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g_free(n->cmbuf);
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}
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}
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if (n->pmrdev) {
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if (n->pmr.dev) {
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host_memory_backend_set_mapped(n->pmrdev, false);
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host_memory_backend_set_mapped(n->pmr.dev, false);
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}
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}
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msix_uninit_exclusive_bar(pci_dev);
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msix_uninit_exclusive_bar(pci_dev);
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}
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}
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static Property nvme_props[] = {
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static Property nvme_props[] = {
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DEFINE_BLOCK_PROPERTIES(NvmeCtrl, namespace.blkconf),
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DEFINE_BLOCK_PROPERTIES(NvmeCtrl, namespace.blkconf),
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DEFINE_PROP_LINK("pmrdev", NvmeCtrl, pmrdev, TYPE_MEMORY_BACKEND,
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DEFINE_PROP_LINK("pmrdev", NvmeCtrl, pmr.dev, TYPE_MEMORY_BACKEND,
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HostMemoryBackend *),
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HostMemoryBackend *),
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DEFINE_PROP_STRING("serial", NvmeCtrl, params.serial),
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DEFINE_PROP_STRING("serial", NvmeCtrl, params.serial),
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DEFINE_PROP_UINT32("cmb_size_mb", NvmeCtrl, params.cmb_size_mb, 0),
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DEFINE_PROP_UINT32("cmb_size_mb", NvmeCtrl, params.cmb_size_mb, 0),
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@ -151,7 +151,11 @@ typedef struct NvmeCtrl {
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uint16_t temperature;
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uint16_t temperature;
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uint8_t smart_critical_warning;
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uint8_t smart_critical_warning;
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HostMemoryBackend *pmrdev;
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struct {
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HostMemoryBackend *dev;
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bool cmse;
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hwaddr cba;
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} pmr;
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uint8_t aer_mask;
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uint8_t aer_mask;
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NvmeRequest **aer_reqs;
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NvmeRequest **aer_reqs;
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