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hw/intc/grlib_irqmp: implements the multiprocessor status register

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This implements the multiprocessor status register in grlib-irqmp and
bind it to a start signal, which will be later wired in leon3-generic
to start a cpu.

The EIRQ and BA bits are not implemented.

Based on https://gaisler.com/doc/gr712rc-usermanual.pdf, §8.3.5.

Co-developed-by: Frederic Konrad <konrad.frederic@yahoo.fr>
Signed-off-by: Clément Chigot <chigot@adacore.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20240131085047.18458-4-chigot@adacore.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
This commit is contained in:
Clément Chigot 2024-01-31 09:50:41 +01:00 committed by Philippe Mathieu-Daudé
parent 6bf1478543
commit 7ed9a5f626
1 changed files with 32 additions and 3 deletions
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35
hw/intc/grlib_irqmp.c
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@ -52,6 +52,10 @@
#define FORCE_OFFSET 0x80
#define EXTENDED_OFFSET 0xC0
/* Multiprocessor Status Register */
#define MP_STATUS_CPU_STATUS_MASK ((1 << IRQMP_MAX_CPU)-2)
#define MP_STATUS_NCPU_SHIFT 28
#define MAX_PILS 16
OBJECT_DECLARE_SIMPLE_TYPE(IRQMP, GRLIB_IRQMP)
@ -65,6 +69,7 @@ struct IRQMP {
unsigned int ncpus;
IRQMPState *state;
qemu_irq start_signal[IRQMP_MAX_CPU];
qemu_irq irq;
};
@ -72,6 +77,7 @@ struct IRQMPState {
uint32_t level;
uint32_t pending;
uint32_t clear;
uint32_t mpstatus;
uint32_t broadcast;
uint32_t mask[IRQMP_MAX_CPU];
@ -182,10 +188,12 @@ static uint64_t grlib_irqmp_read(void *opaque, hwaddr addr,
return state->force[0];
case CLEAR_OFFSET:
case MP_STATUS_OFFSET:
/* Always read as 0 */
return 0;
case MP_STATUS_OFFSET:
return state->mpstatus;
case BROADCAST_OFFSET:
return state->broadcast;
@ -224,8 +232,9 @@ static uint64_t grlib_irqmp_read(void *opaque, hwaddr addr,
static void grlib_irqmp_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
IRQMP *irqmp = opaque;
IRQMP *irqmp = opaque;
IRQMPState *state;
int i;
assert(irqmp != NULL);
state = irqmp->state;
@ -258,7 +267,18 @@ static void grlib_irqmp_write(void *opaque, hwaddr addr,
return;
case MP_STATUS_OFFSET:
/* Read Only (no SMP support) */
/*
* Writing and reading operations are reversed for the CPU status.
* Writing "1" will start the CPU, but reading "1" means that the CPU
* is power-down.
*/
value &= MP_STATUS_CPU_STATUS_MASK;
for (i = 0; i < irqmp->ncpus; i++) {
if ((value >> i) & 1) {
qemu_set_irq(irqmp->start_signal[i], 1);
state->mpstatus &= ~(1 << i);
}
}
return;
case BROADCAST_OFFSET:
@ -325,6 +345,8 @@ static void grlib_irqmp_reset(DeviceState *d)
memset(irqmp->state, 0, sizeof *irqmp->state);
irqmp->state->parent = irqmp;
irqmp->state->mpstatus = ((irqmp->ncpus - 1) << MP_STATUS_NCPU_SHIFT) |
((1 << irqmp->ncpus) - 2);
}
static void grlib_irqmp_realize(DeviceState *dev, Error **errp)
@ -338,6 +360,13 @@ static void grlib_irqmp_realize(DeviceState *dev, Error **errp)
}
qdev_init_gpio_in(dev, grlib_irqmp_set_irq, MAX_PILS);
/*
* Transitionning from 0 to 1 starts the CPUs. The opposite can't
* happen.
*/
qdev_init_gpio_out_named(dev, irqmp->start_signal, "grlib-start-cpu",
IRQMP_MAX_CPU);
qdev_init_gpio_out_named(dev, &irqmp->irq, "grlib-irq", 1);
memory_region_init_io(&irqmp->iomem, OBJECT(dev), &grlib_irqmp_ops, irqmp,
"irqmp", IRQMP_REG_SIZE);